Datasheet

VOLUME CONTROL REGISTER (0x0E)
MODULATION LIMIT REGISTER (0x10)
TAS5086
www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008
Bit D7: Reserved = 1
Bit D6: If 0, then biquad 1 (BQ1) volume compensation part only is disabled (default).
If 1, then BQ1 volume compensation is enabled.
Bit D5: If 0, disable 38-kHz input sample rate detection (38 kHz should be set manually by the
microprocessor).
If 1, enable 38-kHz input sample rate detection.
Bit D4: Reserved = 1
Bit D3: Not used
Bits D2 – D0: Volume slew rate
Table 10. Volume Control Register (0x0E)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
1 – – – – – – – Reserved (must be 1)
– 0 – – – – – – Disable biquad volume compensation
– 1 – – – – – – Enable biquad volume compensation
– – 1 – – – – – Enable 38-kHz input sample rate detection
– – 0 – – – – – Disable 38-kHz input sample rate detection
– – – 1 – – – – Reserved (must be 1)
– – – – – 0 0 0 Volume Slew 512 Steps
– – – – – 0 0 1 Volume Slew 1024 Steps
– – – – – 0 1 0 Volume Slew 2048 Steps
– – – – – 0 1 1 Volume Slew 256 Steps
Set modulation limit. See the appropriate power stage data sheet for recommended modulation limits.
Table 11. Modulation Limit Register (0x10)
D7 D6 D5 D4 D3 D2 D1 D0 LIMIT MIN WIDTH MODULATION
[DCLKs] [DCLKs] LIMIT
– – – – – 0 0 0 1 2 99.2%
– – – – – 0 0 1 2 4 98.4%
– – – – – 0 1 0 3 6 97.7%
– – – – – 0 1 1 4 8 96.9%
– – – – – 1 0 0 5 10 96.1%
– – – – – 1 0 1 6 12 95.3%
– – – – – 1 1 0 7 14 94.5%
– – – – – 1 1 1 8 16 93.8%
Copyright © 2005 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): TAS5086