Datasheet

23
22
SCLK
24Clks
LRCLK
LeftChannel
24-BitMode
1
20-BitMode
16-BitMode
15
14
MSB LSB
SCLK
24Clks
RightChannel
MSB
2-ChannelRight-JustifiedStereoInput(24-Bit TransferWordSize)
T0092-03
5
19 18
1
5
19 18
1
5
0
0
0
2
2
2
6
6
6
15
14
15
14
23
22 1
15
14
5
19 18
1
5
19 18
1
5
0
0
0
2
2
2
6
6
6
15
14
15
14
LSB
I
2
C SERIAL CONTROL INTERFACE
GENERAL I
2
C OPERATION
TAS5086
SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com
Figure 21. Right-Justified 48-f
S
Bit Format
The TAS5086 has a bidirectional Inter IC (I
2
C) interface that is compatible with the I
2
C bus protocol and supports
both single- and multiple-byte write and read operations. The control interface is used to program the registers of
the device and to read device status.
The TAS5086 supports wait-state insertions by other I
2
C devices on the bus. However, the TAS5086 performs all
I
2
C operations without I
2
C wait cycles.
The TAS5086 supports standard-mode I
2
C bus operation (100 kHz maximum) and fast I
2
C bus operation (400
kHz maximum).
The I
2
C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte
(8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and stop conditions.
A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 22 . The
master generates the 7-bit slave address and the read/write (R/ W) bit to open communication with another
device and then wait for an acknowledge condition. The TAS5086 holds SDA low during the acknowledge clock
period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence.
Each device is addressed by a unique 7-bit slave address plus R/ W bit (1 byte). All compatible devices share the
same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for
the SDA and SCL signals to set the HIGH level for the bus.
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