Datasheet

23
22
SCLK
24Clks
LRCLK
LeftChannel
24-BitMode
1
19 18
20-BitMode
16-BitMode
15
14
MSB LSB
24Clks
RightChannel
2-ChannelI S(PhilipsFormat)StereoInput/Output(24-Bit TransferWordSize)
2
T0092-01
3
2
5
4
9 8
17
16
1
0
0
4
5
13
12
1
09 8
23
22
SCLK
1
19 18
15
14
MSB LSB
3
2
5
4
9 8
17
16
1
0
4
5
13
12
1
09 8
LEFT-JUSTIFIED
TAS5086
www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008
Figure 17. I
2
S 48-f
S
Format
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 64
f
S
is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles.
The data is written MSB-first and is valid on the rising edge of the bit clock. The TAS5086 masks unused trailing
data bit positions.
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