Datasheet

SERIAL INTERFACE CONTROL AND TIMING
I
2
S TIMING
23 22
SCLK
32 Clks
LRCLK (Note Reversed Phase) Left Channel
24-Bit Mode
9 8 5 4 1 0
19 18
20-Bit Mode
5 4 1 0
16-Bit Mode
1 015 14
MSB LSB
23 22
SCLK
32 Clks
Right Channel
9 8 5 4 1 0
19 18 5 4 1 0
1 015 14
MSB LSB
2-Channel I
2
S (Philips Format) Stereo Input/Output
T0034-04
TAS5086
SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com
I
2
S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 64 f
S
is used
to clock in the data. A delay of one bit clock occurs from the time the LRCLK signal changes state to the first bit
of data on the data lines. The data is written MSB-first and is valid on the rising edge of the bit clock. The
TAS5086 masks unused trailing data bit positions.
Figure 16. I
2
S 64-f
S
Format
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