Datasheet

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SLAS328 − SEPTEMBER 2001
7
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functional description (continued)
reset
The reset signal for the TAS5010 must be applied whenever toggling the M_S, DBSPD signal. This reset is
asynchronous. See Figure 3 for reset timing. To initiate the reset sequence the RESET
pin is asserted low. As
long as the pin is held low the chip is in the reset state. During this reset time the PWM outputs are hard-muted
(P-outputs held low and M-outputs held high) and the PWM outputs valid pins (VALID_L. VALID_R) are held
low. Assuming PDN
is high, the rising edge of the reset pulse begins chip initialization. After the initialization
time, the TAS5010 begins normal operation.
Initialization
Normal
Operation
RESET
PDN
Normal Operation
5 ms max
VALID_L
VALID_R
Figure 3. Reset Timing
power down
When PDN is low (see Figure 4), both the PLL and the oscillator are shut down. Note that power down is an
asynchronous operation. To place the device in total power-down mode, both RESET
and PDN must be held
low. As long as these pins are held low, the chip is in the power-down state and the PWM outputs are hard muted
with the P outputs held low and the M outputs held high. to place the device back into normal mode, see the
power up section.
NOTE:
In order for the dynamic logic to be properly powered down, the clocks should not be stopped before
the PDN
pin goes low. Otherwise, the device may drain additional supply current.
Initialization
Chip
Power-Down
PDN
and RESET
Normal Operation
Normal
Operation
VALID
Figure 4. Power-Down Timing
mute
The TAS5010 provides a mute function that is used when the MUTE
pin is asserted low. See Table 2 for mute
description. This mute is a quiet mute; that is, the mute is accomplished by outputting a zero value waveform
in which both sides of the differential PWM outputs have a 50% duty cycle (see Figure 5 for mute timing.
Table 2. Mute Description
MUTE P OUTPUTS M OUTPUTS DESCRIPTION
0 50% duty cycle 50% duty cycle Mute
1 DATA DATA Normal operation