Datasheet

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SLAS328 − SEPTEMBER 2001
14
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PARAMETER MEASUREMENT INFORMATION
t
h(SDIN)
t
su(SDIN)
SCLK
SDIN
Figure 11. Right-Justified, IIS, Left-Justified Serial Protocol Timing
t
su(LRCLK)
SCLK
LRCLK
NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns)
Figure 12. Right, Left, and IIS Serial Mode Timing Requirement
t
(MSD)
t
(MLRD)
SCLK
LRCLK
(Output)
MCLK
(Output)
Figure 13. Serial Audio Ports Master Mode Timing
t
h(SDIN)
t
su(SDIN)
SCLK
LRCLK
SDIN
t
su(LRCLK)
t
w(FSHIGH)
t
h(LRCLK)
Figure 14. DSP Serial Port Timing