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7.1.2MasterModeLRCLKDivider
7.1.3SCLKINandSCLKOUTClockDivide
7.1.4MCLK,SCLKRatio(MasterModeOnly)
TAS3108,TAS3108IA
AUDIODIGITALSIGNALPROCESSORS
SLES152B–OCTOBER2005–REVISEDNOVEMBER2007
Bits26–24(Y2,Y1,andY0)definetheratiobetweenSCLKandLRCLK,butonlyhavemeaninginthe
clock-mastermodewhereLRCLKisanoutput.Intheclock-slavemode,LRCLKisaninput.
Y2Y1Y0DESCRIPTION
000LRCLKout=SCLK/32
001LRCLKout=SCLK/64
010LRCLKout=SCLK/128
011LRCLKout=SCLK/192
100LRCLKout=SCLK/256
101LRCLKout=SCLK/384
110LRCLKout=SCLK/512
111LRCLKout=SCLK/32
Bits21–19(X2,X1,andX0)definetheratiobetweenSCLKINandSCLKOUT.Thesecontrolbitsareonly
usedwhentheinputandoutputratesaredifferent,whichcanhappenifTDManddiscretemodesareboth
used(forexample,inputisTDMandoutputisdiscrete).Normally,thesebitsaresetto000,sothat
SCLKOUT1(inputSCLK)andSLCKOUT2(outputSCLK)arethesame.(NotethatSCLKINisnotthe
inputSCLK,butisusedinclock-slavemodetoderiveSCLKOUT1.)
X2X1X0DESCRIPTION
000XMUXout=IMS_MUX(master/slaveSCLK)
001XMUXout=IMS_MUX/2
010XMUXout=IMS_MUX/3
011XMUXout=IMS_MUX/4
100XMUXout=IMS_MUX/6
101XMUXout=IMS_MUX/8
110XMUXout=IMS_MUX/16
111XMUXout=IMS_MUX/32
Bits18–16(Z2,Z1,andZ0)definetheratiobetweenMCLKandSCLKwhentheTAS3108/TAS3108IAis
theclockmaster.Inclock-slavemode,thesebitsaredon'tcare.
Z2Z1Z0DESCRIPTION
000ZMUXout=MCLK(MCLKIorcrystaloscillator)
001ZMUXout=MCLK/2
010ZMUXout=MCLK/3
011ZMUXout=MCLK/4
100ZMUXout=MCLK/6
101ZMUXout=MCLK/8
110ZMUXout=MCLK/16
111ZMUXout=MCLK/32
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