Datasheet
www.ti.com
TAS3108,TAS3108IA
AUDIODIGITALSIGNALPROCESSORS
SLES152B–OCTOBER2005–REVISEDNOVEMBER2007
Table6-2.MasterAddresses
BASEADDRESSCS0R/W MASTERADDRESS
101000000xA0
101000010xA1
101000100xA2
101000110xA3
ThefollowingisanexampleuseoftheI
2
CmasteraddresstoaccessanexternalEEPROM.The
TAS3108/TAS3108IAcanaddressuptotwoEEPROMsdependingonthestateofCS0.Initially,the
TAS3108/TAS3108IAcomesupinI
2
Cmastermode.Ifitfindsamemorysuchasthe24C512EEPROM,it
readstheheadersanddataaspreviouslydescribed.InthisI
2
Cmastermode,theTAS3108/TAS3108IA
addressestheEEPROMsasshowninTable6-3andTable6-4.
Table6-3.EEPROMAddressI
2
CTAS3108/TAS3108IAMasterMode=0xA1/A0
A0
MSBCS0R/W
(EEPROM)
10100001/0
Table6-4.EEPROMAddressI
2
CTAS3108/TAS3108IAMasterMode=0xA3/A2
A0
MSBCS0R/W
(EEPROM)
10100011/0
RandomI
2
CTransactions
SupplyingasubaddressforeachsubaddresstransactionisreferredtoasrandomI
2
Caddressing.For
randomI
2
Creadcommands,theTAS3108/TAS3108IArespondswithdata,abyteatatime,startingatthe
subaddressassigned,aslongasthemasterdevicecontinuestorespondwithacknowledges.Ifagiven
subaddressdoesnotuseall32bits,theunusedbitsarereadaslogic0.I
2
Cwritecommands,however,
aretreatedinaccordancewiththedataassignmentforthataddressspace.Ifawritecommandisreceived
forabiquadsubaddress,forexample,theTAS3108/TAS3108IAexpectstoseefive32-bitwords.Iffewer
thanfivedatawordshavebeenreceivedwhenastopcommand(oranotherstartcommand)isreceived,
thedatareceivedisdiscarded.
SequentialI
2
CTransactions
TheTAS3108/TAS3108IAalsosupportssequentialI
2
Caddressing.Forwritetransactions,ifasubaddress
isissuedfollowedbydataforthatsubaddressandthe15subaddressesthatfollow,asequentialI
2
Cwrite
transactionhastakenplace,andthedataforall16subaddressesissuccessfullyreceivedbythe
TAS3108/TAS3108IA.ForI
2
Csequentialwritetransactions,thesubaddressthenservesasthestart
address,andtheamountofdatasubsequentlytransmittedbeforeastoporstartistransmitteddetermines
howmanysubaddressesarewrittento.Aswastrueforrandomaddressing,sequentialaddressing
requiresthatacompletesetofdatabetransmitted.Ifonlyapartialsetofdataiswrittentothelast
subaddress,thedataforthelastsubaddressisdiscarded.However,allotherdatawrittenisaccepted;just
theincompletedataisdiscarded.
Sequentialreadtransactionsdonothaverestrictionsonoutputtingonlycompletesubaddressdatasets.
Ifthemasterdoesnotissueenoughdata-receivedacknowledgestoreceiveallthedataforagiven
subaddress,themasterdevicedoesnotreceiveallthedata.
Ifthemasterdeviceissuesmoredata-receivedacknowledgesthanrequiredtoreceivethedataforagiven
subaddress,themasterdevicesimplyreceivescompleteorpartialsetsofdata,dependingonhowmany
data-receivedacknowledgesareissuedfromthesubaddress(es)thatfollow.I
2
Creadtransactions,both
sequentialandrandom,canimposewaitstates.
MicroprocessorController 30SubmitDocumentationFeedback
Not Recommended for New Designs