Datasheet

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TAS3108,TAS3108IA
AUDIODIGITALSIGNALPROCESSORS
SLES152B–OCTOBER2005–REVISEDNOVEMBER2007
Whentheserialaudioport(SAP)isinthemastermode,theSAPusestheMCLKIorXTALImasterclock
todrivetheserialportclocksSCLKOUT1,SLCKOUT2,andLRCLK.WhentheSAPisintheslavemode,
LRCLKisaninputandSCLKOUT2andSCLKOUT1arederivedfromSCLKIN.AsshowninFigure5-2,
SCLKOUT1clocksdataintotheinputSAPandSCLKOUT2clocksdatafromtheoutputSAP.Twodistinct
clocksarerequiredtosupportTDM-to-discreteanddiscrete-to-TDMdata-formatconversions.Suchformat
conversionsalsorequirethatSCLKINbethehigher-valuedbit-clockfrequency.ForTDM-in/discrete-out
formatconversions,SCLKINmustbeequaltotheinputbitclock.Fordiscrete-in/TDM-outformat
conversions,SCLKINmustbeequaltotheoutputbitclock.ThefrequencysettingsforSCLKOUT1,
SCLKOUT2,andLRCLKintheSAPmastermode,aswellastheSAPmaster/slavemodeselection,are
allcontrolledbyI
2
Ccommands.Table5-3liststhedefaultsettingsatpowerturnonorafterareceived
reset.
Table5-3.TAS3108/TAS3108IAClockDefaultSettings
CLOCKDEFAULTSETTING
SCLKOUT1SCLKIN
SCLKOUT2SCLKIN
MCLKOMCLKIorXTALI
LRCLKInput
AudioDSPclockSetbypinsPLL0andPLL1
MicroprocessorclockSetbypinMICROCLK_DIV
PLLmultiplyratio11
I
2
CsamplingclockN=0
I
2
CmasterSCLM=8
TheselectionsprovidedbythededicatedTAS3108/TAS3108IAinputpinsandtheprogrammablesettings
providedbyI
2
CsubaddresscommandsgivetheTAS3108/TAS3108IAavarietyofclockingoptions.
However,thefollowingclockingrestrictionsmustbeadheredto:
•MCLKIorXTALI≥128f
S
NOTE
ForsomeTDMmodes,MCLKIorXTALImustbe≥256f
S
•AudioDSPclock<136MHz
•Microprocessorclock/20≥I
2
CSCLclock
•Microprocessorclock≤34MHz
•I
2
Coversampleclock/20≥I
2
CSCLclock
•XTALI≤20MHz
•MCLKI≤25MHz
Aslongastheserestrictionsaremet,allotherclockingoptionsareallowed.
SeeSection7.1forinformationonprogrammingtheclockregister.
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