Datasheet

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SCLKIN

OSC

PLL and Clock Management

2xSDA

Audio DSP Core

MCLKO PLL1 PLL0 SCLKOUT1 LRCLK MICROCLK_DIV SCLKOUT2

2xSCL

8-Bit

WARP

8051 Microprocessor

1/2

N

1/(M+1)

I

2

C

Master/Slave

Controller

÷10

Master

SCL

MCLKI XTALI XTALO

M

U

X

÷Y = 64

DEFAULT

M

U

X

M

U

X

÷2 ÷2

M

U

X

MCLK

PLL

× 11

M

U

X

÷2 ÷2

M

U

X

÷4

M

U

X

Input

SAP

Microprocessor

and

I

2

C Bus Controller

Output

SAP

N = 0 (Default)

÷ X = 1

DEFAULT

Oversample Clock

B0078-01

÷ Z = 2

DEFAULT

PLL2

M = 8 (Default)

TAS3108,TAS3108IA

AUDIODIGITALSIGNALPROCESSORS

SLES152B–OCTOBER2005–REVISEDNOVEMBER2007

Figure5-2.DPLLandClockManagementBlockDiagram

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Not Recommended for New Designs