Datasheet

www.ti.com
TAS3108,TAS3108IA
AUDIODIGITALSIGNALPROCESSORS
SLES152B–OCTOBER2005–REVISEDNOVEMBER2007
Table5-1.PLL2,PLL1,andPLL0PinConfigurationControls
PLL2PLL1PLL0AUDIODSPCLOCK
00011×MCLK/1
00111×MCLK/2
01011×MCLK/4
011Reserved
1XXReserved
AudioDSPclockoraudioDSPclock/4isusedtoclocktheon-chipmicroprocessor.Theinputpin
MICROCLK_DIVmakesthisclockchoice.Alogic-1inputlevelonthispinselectstheaudioDSPclockfor
themicroprocessorclock;alogic-0inputlevelonthispinselectstheaudioDSPclock/4forthe
microprocessorclock.Themicroprocessorclockmustbe≤34MHz.
Table5-2.MICROCLK_DIVPinConfigurationControl
MICROCLK_DIVMICROPROCESSORCLOCK
0AudioDSPclock/4
1AudioDSPclock
NOTE
ThestateofPLL0,PLL1,PLL2,andMICROCLK_DIVcanonlybechangedwhilethe
TAS3108orTAS3108IARESETpinisheldlow.
TheTAS3108/TAS3108IAonlysupportsdynamicsample-ratechangesbetweenanyofthesupported
samplefrequencieswhenafixed-frequencymasterclockisprovided.Duringdynamicsample-rate
changes,theTAS3108/TAS3108IAremainsinnormaloperationandtheregistercontentsarepreserved.
Toavoidproducingaudioartifactsduringthesample-ratechanges,avolumeormutecontrolcanbe
includedintheapplicationfirmwarethatmutestheoutputsignalduringthesample-ratechange.The
fixed-frequencyclockcanbeprovidedbyacrystal,attachedtoXTLIandXTLO,oranexternal3.3-V
fixed-frequencyTTLsourceattachedtoMCLKI.
WhentheTAS3108/TAS3108IAisusedinasysteminwhichthemasterclockfrequency(f
MCLK
)can
change,theTAS3108/TAS3108IAmustberesetduringthefrequencychange.Inthesecases,the
procedureshowninFigure5-1shouldbeused.
ClockControls 20SubmitDocumentationFeedback
Not Recommended for New Designs