Datasheet

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SDIN1
SDOUT1
Sample Time N Sample Time N + 1 Sample Time N + 2
1
st
Half − Sample Time N
Serial
Rx
Regs
Input
Holding
Regs
Input
Holding
Regs
A
Channel 1
U
VB
SDIN2
SDOUT2
C
Channel 2
W
XD
SDIN3
SDOUT3
E
Channel 3
Y
Z
F
G
H
SDIN1
SDOUT1
Sample Time N Sample Time N + 1 Sample Time N + 2
2
nd
Half − Sample Time N
Serial
Rx
Regs
Input
Holding
Regs
Input
Holding
Regs
A U
VB
SDIN2
SDOUT2
C
XD
SDIN3
SDOUT3
E Y
Z
F
SDIN4
G
H
SDIN1
SDOUT1
Sample Time N Sample Time N + 1 Sample Time N + 2
Sample Time N + 1
Serial
Rx
Regs
Input
Holding
Regs
Input
Holding
Regs
A U
VB
SDIN2
SDOUT2
C
XD
SDIN3
SDOUT3
E Y
ZF
G
H
SDIN1
SDOUT1
Sample Time N Sample Time N + 1 Sample Time N + 2
Sample Time N + 2
Serial
Rx
Regs
Input
Holding
Regs
Input
Holding
Regs
A U
VB
SDIN2
SDOUT2
C
XD
SDIN3
SDOUT3
E Y
ZF
G
H
W
WW
SDIN4
SDIN4
SDIN4
B0076-01
Input
Mux
Output
Mux
Input
Mux
Output
Mux
Input
Mux
Output
Mux
Input
Mux
Output
Mux
Channel 1
Channel 2
Channel 3
Channel 1
Channel 2
Channel 3
Channel 1
Channel 2
Channel 3
TAS3108,TAS3108IA
AUDIODIGITALSIGNALPROCESSORS
SLES152B–OCTOBER2005–REVISEDNOVEMBER2007
Figure3-7.SAPInput-to-OutputLatency
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Not Recommended for New Designs