Datasheet

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3.8.32ChannelRightJustifiedTiming
23
22
SCLK
32Clks
LRCLK
LeftChannel
24-BitMode
1
20-BitMode
16-BitMode
15
14
MSB LSB
SCLK
32Clks
RightChannel
2-ChannelRight-Justified(SonyFormat)StereoInput
T0034-03
19 18
1
19 18
1
0
0
0
15
14
15
14
23
22 1
15
14
MSB LSB
19 18
1
19 18
1
0
0
0
15
14
15
14
3.8.4TDMModes
TAS3108,TAS3108IA
AUDIODIGITALSIGNALPROCESSORS
SLES152B–OCTOBER2005–REVISEDNOVEMBER2007
In2-channelright-justifiedtiming,LRCLKisHIGHwhenleftchanneldataistransmittedandLOWwhen
rightchanneldataistransmitted.SCLKisabitclockrunningat64×f
S
,whichclocksineachbitofthe
data.Thefirstbitofdataappearsonthedatalines8bit-clockperiods(for24-bitdata)afterLRCLK
toggles.Intheright-justifiedmode,thelastbitclockbeforeLRCLKtransitionsalwaysclockstheLSBof
data.ThedataiswrittenMSBfirstandisvalidontherisingedgeofthebitclock.The
TAS3108/TAS3108IAmasksunusedleadingdata-bitpositions.
Figure3-4.Rightjustified64-f
S
Format
TheTDMmodesontheTAS3108/TAS3108IAprovideleftjustifiedandI
2
Sformats.EachwordintheTDM
datastreamadherestothebitplacementshowninFigure3-5andFigure3-6.Twocasesare
illustrated—anI
2
Sdataformatandaleft-justifieddataformat.
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