Datasheet

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3.8.22ChannelLeftJustifiedTiming
23
22
SCLK
32Clks
LRCLK
LeftChannel
24-BitMode
1
19 18
20-BitMode
16-BitMode
15
14
MSB LSB
32Clks
RightChannel
2-ChannelLeft-JustifiedStereoInput
T0034-02
4
5
9 8
1
4
5
1
0
0
0
23
22 1
19 18
15
14
MSB LSB
4
5
9 8
1
4
5
1
0
0
0
SCLK
TAS3108,TAS3108IA
AUDIODIGITALSIGNALPROCESSORS
SLES152B–OCTOBER2005–REVISEDNOVEMBER2007
In2channelleftjustifiedtiming,LRCLKisHIGHwhenleftchanneldataistransmittedandLOWwhen
rightchanneldataistransmitted.SCLKisabitclockrunningat64×f
S
whichclocksineachbitofthe
data.ThefirstbitofdataappearsonthedatalinesatthesametimeLRCLKtoggles.Thedataiswritten
MSBfirstandisvalidontherisingedgeofthebitclock.TheTAS3108/TAS3108IAmasksunusedtrailing
data-bitpositions.
Figure3-3.Leftjustified64-f
S
Format
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