Datasheet

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3.8.12channelI
2
STiming
23 22
SCLK
32 Clks
LRCLK (Note Reversed Phase) Left Channel
24-Bit Mode
9 8 5 4 1 0
19 18
20-Bit Mode
5 4 1 0
16-Bit Mode
1 015 14
MSB LSB
23 22
SCLK
32 Clks
Right Channel
9 8 5 4 1 0
19 18 5 4 1 0
1 015 14
MSB LSB
2-Channel I
2
S (Philips Format) Stereo Input/Output
T0034-04
TAS3108,TAS3108IA
AUDIODIGITALSIGNALPROCESSORS
SLES152B–OCTOBER2005–REVISEDNOVEMBER2007
Followingareset,ensurethattheclockregister(0x00)iswrittenbeforeperformingvolume,treble,orbass
updates.
CommandstoreconfiguretheSAPcanbeaccompaniedbymuteandunmutecommandsforquiet
operation.However,caremustbetakentoensurethatthemutecommandhascompletedbeforetheSAP
iscommandedtoreconfigure.Similarly,theTAS3108/TAS3108IAshouldnotbecommandedtounmute
untilaftertheSAPhascompletedareconfiguration.ThereasonforthisisthatanSAPconfiguration
changewhileavolumeorbassortrebleupdateistakingplacecancausetheupdatenottobecompleted
properly.
WhentheTAS3108/TAS3108IAistransmittingserialdata,itusesthenegativeedgeofSCLKtooutputa
newdatabit.TheTAS3108/TAS3108IAsamplesincomingserialdataontherisingedgeofSCLK.The
TAS3108/TAS3108IAonlysupportsTDM,leftjustified,rightjustified,andI
2
Sformats.
In2channelI
2
Stiming,LRCLKisLOWwhenleftchanneldataistransmittedandHIGHwhenright
channeldataistransmitted.SCLKisabitclockrunningat64×f
S
,whichclocksineachbitofthedata.
ThereisadelayofonebitclockfromthetimetheLRCLKsignalchangesstatetothefirstbitofdataon
thedatalines.ThedataiswrittenMSBfirstandisvalidontherisingedgeofthebitclock.The
TAS3108/TAS3108IAmasksunusedtrailingdata-bitpositions.
Figure3-2.I
2
S64-f
S
Format
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