Datasheet

1−2
1.2 Terminal Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
SCLKIN
PWRDN
REGULATOR_EN
XTALI (1.8-V logic)
XTALO (1.8-V logic)
AVDD_BYPASS_CAP
A_VDDS (3.3 V)
AVSS
MCLKI
TEST
MICROCLK_DIV
I2C_SDA
I2C_SCL
SDIN1
SDIN2
SDIN3
SDIN4
GPIO0
GPIO1
LRCLK
ORIN
SCLKOUT2
SCLKOUT1
MCLKO
SDOUT3
SDOUT2
VDDS (3.3 V)
SDOUT1
DVDD_BYPASS_CAP
DVSS
I2CM_S
RST
CS1
CS0
PLL1
PLL0
GPIO3
GPIO2
DBT PACKAGE
(TOP VIEW)