Datasheet

2−20
2.3.2.2 I
2
C Slave Mode Operation
The I
2
C slave mode is the mode that must be used if it is required to change configuration parameters (other than
volume via the GPIO pins for the I
2
C master mode) during operation. The I
2
C slave mode is also the only I
2
C mode
that provides access to the spectrum analyzer and VU meter outputs. Configuration downloads from a master device
can be used to replace the I
2
C master mode EEPROM download.
For I
2
C read commands, the TAS3103 responds with data, a byte at a time, starting at the subaddress assigned, as
long as the master device continues to respond with acknowledges. If a given subaddress does not use all 32 bits,
the unused bits are read as logic 0. I
2
C write commands, however, are treated in accordance with the data assignment
for that address space. If a write command is received for a biquad subaddress, the TAS3103 expects to see five
32-bit words. If fewer than five data words have been received when a stop command (or another start command)
is received, the data received is discarded. If a write command is received for a mixer coefficient, the TAS3103
expects to see only one 32-bit word.
Supplying a subaddress for each subaddress transaction is referred to as random I
2
C addressing. The TAS3103 also
supports sequential I
2
C addressing. For write transactions, if a subaddress is issued followed by data for that
subaddress and the fifteen subaddresses that follow, a sequential I
2
C write transaction has taken place, and the data
for all 16 subaddresses is successfully received by the TAS3103. For I
2
C sequential write transactions, the
subaddress then serves as the start address and the amount of data subsequently transmitted, before a stop or start
is transmitted, determines how many subaddresses are written to. As was true for random addressing, sequential
addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last
subaddress, the data for the last subaddress is discarded. However, all other data written is accepted; just the
incomplete data is discarded.
The GPIO subaddresses and most reserved read-only and factory test subaddresses require the downloading of four
bytes of zero-valued spacer data in order to proceed to the next subaddress. However, there are five exceptions to
this rule and Table 2−4 lists the subaddresses of these fexceptions and the number of zero-valued bytes that must
be written.
Table 2−4. Four Byte Write Exceptions—Reserved and Factory-Test I
2
C Subaddresses
SUB-ADDRESS
NUMBER OF ZERO-VALUED BYTES
THAT MUST BE WRITTEN
0xC9 8
0xED 8
0xFD 10 (0xA)
0xFE 2
0xFF 1
The TAS3103 can always receive sequential I
2
C addressing write data without issuing wait states. If it is desired to
download data to all subaddresses using one sequential write transaction, spacer data for the reserved, GPIO,
read-only, and factory-test subaddresses must be supplied as per Table 2−3 and Table 2−4.
The TAS3103 also supports sequential read transactions. When an I
2
C subaddress assignment write transaction is
followed by a read transaction, the TAS3103 outputs the data for that subaddress, and then continue to output data
for the subaddresses that follow as long as the master continues to issue data received acknowledges. Except for
two exceptions, the TAS3103 outputs four bytes of zero-valued data for reserved and factory-test subaddresses. The
subaddresses of the exceptions and the number of bytes supplied by the TAS3103 for each exception are given in
Table 2−5. If a GPIO port is assigned as an output port, a logic 0 bit value is supplied by the TAS3103 for this GPIO
port in response to a read transaction at subaddress 0xEE.
CAUTION: Sequential write transactions must be in ascending subaddress order. The
TAS3103 does not wrap around from subaddress 0xFF to 0x00.
Sequential read transactions wrap around from subaddress 0xFF to 0x00.