Datasheet

2−13
Table 2−1 lists all viable clock selections for a given audio sample rate (LRCLK). The table only includes those clock
choices that allow enough processing throughput to accomplish all tasks within a given sample time (T
s
= 1/LRCLK).
For each entry in the table, the DAP processing time is given in terms of whether the time is greater than 0.5 T
s
(resulting in an input to output delay of 2.5 T
s
), or less than 0.5 T
s
(resulting in an input to output delay of 1.5 T
s
).
Table 2−1 is valid for both master and slave I
2
S modes (bit IMS at subaddress 0xF9 determines I
2
S master/slave
selection—see the DPLL and Clock Management section that follows). For all applications, MCLK must be ≥128
LRCLK (FS). In the I
2
S master mode, MCLK, SCLK (I
2
S bit clock) LRCLK are all harmonically related. Furthermore,
in the I
2
S master mode, if a master clock value given in Table 2−1 is used, the latency realized in performing I
2
S format
conversions, 1.5 samples or 2.5 samples, is stable and fixed over the duration of operation. However, greater care
must be taken for the I
2
S slave mode. In this mode, the device has the proper operational throughput to perform all
required computations as long as MCLK is ≥128 LRCLK. But there is no longer the requirement that MCLK be
harmonically related to SCLK and LRCLK. Values of MCLK could be chosen such that the output dithers between
latencies of 1.5 and 2.5 sample times. There may be cases where part of the data stream output exhibits sample time
latencies of 1.5 T
s
and the other portion of the output data stream exhibits sample time latencies of 2.5 T
s
. To assure
that such cases do not happen in the I
2
S slave mode, the relationships between MCLK and LRCLK given in Table 2−1
should be followed for data format conversions involving the I
2
S format. The MCLKI/XTALI frequencies given in
Table 2−1 (if set to within ±5% of the nominal value shown) assure that the DAP processing time falls above 0.5 T
s
or below 0.5 T
s
with enough margin to assure that there is no race condition between the outputting of data and the
completion of the processing tasks.
Table 2−1. TAS3103 Throughput Latencies vs MCLK and LRCLK
AUDIO
SAMPLE RATE
(LRCLK)
MASTER CLOCK
(2)
(MCLKI/XTALI)
DAP
(1)
CLOCK
(PLL_OUTPUT)
DAP CLOCK
CYCLES/LRC
LK
DAP
PROCESSING
TIME
THROUGHPU
T DELAY
96 kHz 24.576 MHz, 12.288 MHz 135.168 MHz 1408 > T
s
/2 2.5 T
s
88.2 kHz 22.5792 MHz, 11.2896 MHz 124.1856 MHz 1408 > T
s
/2 2.5 T
s
48 kHz
24.576 MHz, 12.288 MHz 135.168 MHz 2816 < T
s
/2 1.5 T
s
48 kHz
24.576 MHz, 12.288 MHz, 6.144 MHz 67.584 MHz 1408 > T
s
/2 2.5 T
s
44.1 kHz
22.5792 MHz, 11.2896 MHz 124.1856 MHz 2816 < T
s
/2 1.5 T
s
44.1 kHz
22.5792 MHz, 11.2896 MHz, 5.6448 MHz 62.0928 MHz 1408 > T
s
/2 2.5 T
s
32 kHz
16.384 MHz, 8.192 MHz 90.112 MHz 2816 < T
s
/2 1.5 T
s
32 kHz
16.384 MHz, 8.192 MHz, 4.096 MHz 45.056 MHz 1408 > T
s
/2 2.5 T
s
24.576 MHz, 12.2858 MHz 135.168 MHz 5632 < T
s
/2 1.5 T
s
24 kHz
24.576 MHz, 12.2858 MHz, 6.144 MHz 67.584 MHz 2816 < T
s
/2 1.5 T
s
24 kHz
12.288 MHz, 6.144 MHz, 3.072 MHz 33.792 MHz 1408 > T
s
/2 2.5 T
s
22.5792 MHz, 11.2896 MHz 124.1856 MHz 5632 < T
s
/2 1.5 T
s
22.05 kHz
22.5792 MHz, 11.2896 MHz, 5.6448 MHz 62.0928 MHz 2816 < T
s
/2 1.5 T
s
22.05 kHz
11.2896 MHz, 5.6448 MHz, 2.8224 MHz 31.0464 MHz 1408 > T
s
/2 2.5 T
s
24.576 MHz, 12.288 MHz 135.168 MHz 16896 < T
s
/2 1.5 T
s
8 kHz
24.576 MHz, 12.288 MHz, 6.144 MHz 67.584 MHz 8448 < T
s
/2 1.5 T
s
8 kHz
12.288 MHz, 6.144 MHz, 3.072 MHz 33.792 MHz 4224 < T
s
/2 1.5 T
s
6.144 MHz, 3.072 MHz, 1.536 MHz 16.896 MHz 2112 > T
s
/2 2.5 T
s
NOTES: 1. DAP clock is the internal digital audio processor clock. It is equal to 11 × MCLK1/XTALI, 11/2 × MCLKI/XTALI, or 11/4 × MCLKI/XTALI
(as determined by a bit field in I
2
C subaddress 0xF9). The DAP clock must always be greater than or equal to 1400 F
S
(LRCLK).
2. Unless in PLL bypass, MCLKI must be ≤ 20 MHz.
3. XTALI must always be ≤ 20 MHz.