Datasheet

2−12
L2
LRCLK
R2 L3 R3 L4 R4
L1, R1
L2, R2 L3, R3
L0 R0 L1 R1 L2
L1, R1 L2, R2
L3, R3
R0
L1 R1 L2 R2 L3
SDIN
Processing Cycle
Load Output Holding Registers
Holding Register ⇒ Output Serial Registers
SDOUT
2.5
Cycle
Delay
1.5
Cycle
Delay
Processing Cycle
Load Output Holding Registers
Holding Register ⇒ Output Serial Registers
SDOUT
(a) Left-Justified Input / I
2
S Output
L2
LRCLK
R2 L3 R3 L4 R4
L1, R1
L2, R2 L3, R3
L0 R0 L1 R1 L2
L1, R1 L2, R2
L3, R3
R0
L1 R1 L2 R2 L3
SDIN
Processing Cycle
Load Output Holding Registers
Holding Register ⇒ Output Serial Registers
SDOUT
2.5
Cycle
Delay
1.5
Cycle
Delay
Processing Cycle
Load Output Holding Registers
Holding Register ⇒ Output Serial Registers
SDOUT
(b) I
2
S Input / Left-Justified Output
Figure 2−13. SAP Input-to-Output Latency for I
2
S Format Conversions
The delay from input to output can thus be either 1.5 or 2.5 sample times when data format conversions are performed
that involves the I
2
S format. However, which delay time is obtained for a particular application is determinable and
fixed for that application, providing care is taken in the selection of MCLKI/XTALI with respect to the incoming sample
clock LRCLK.