Datasheet
1−21
Word Size Code
†
I
2
S FORMAT, CLOCK MANAGEMENT, AND I
2
C M AND N ASSIGNMENTS
n[2:0]
02
m[3:0]
36
OSC
XTALI
0
1
2
3
MCLKO
0
1
2
PLL0
x11
PLL
MUX
MUX
PLL
BYPASS
Digital Audio
Processor
Clock
PLL[1:0]
1
0
MUX
MICROCLK_DIV
1/(M+1)
I2C_SDA
0
1
2
3
4
5
6
7
MUX
MUX
CRYSTAL
0
1
2
3
MUX
1
0
MUX
0
1
2
3
4
5
6
7
MUX
0
1
2
3
4
5
6
7
MUX
1
0
MUX
0
1
SCLKIN
SCLKOUT2 SCLKOUT1
LRCLK
Microprocessor
Clock
0xFB
0xF9
DWFMT (Data Word Format)
Word Size
32 Bit
16 Bit
18 Bit
20 Bit
24 Bit
32 Bit
IM0/OM0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Mode
Discrete, Left Justified
Discrete, Left Justified
Discrete, Right Justified
Discrete, I
2
S
Discrete, 16 − Bit Packed
TDM_LJ_8
TDM_LJ_6
TDM_LJ_4
TDM_I2S_8
TDM_I2S_6
TDM_I2S_4
TDM_20Bit_6
6 Ch, Single Chip, Crystal (LJ)
6 Ch, Single Chip (LJ)
6 Ch, Single Chip, Crystal (I
2
S)
6 Ch, Single Chip, 20 − Bit
AB assigns TDM time slots for those TDM
outputs involving two TAS3103s. For these
output formats, one of the TAS3103 chips
must be defined as AB = 0. The other
TAS3103 chip must be defined as AB = 1.
MCLKI
IW2/OW2
0
0
0
0
1
1
1
1
IW1/OW1
0
0
1
1
0
0
1
1
IW0/OW0
0
1
0
1
0
1
0
1
AckIOMAck
OW[2:0]
15
IW[2:0]
0
AB
14 13 11 10 8
7
DWFMT
815
Ackz[2:0]IMS x[2:0]ICSAck x[2:0]y[2:0]w[1:0]000AckSub-AddrAckSlave AddrS
161819212223242627282931
OM[3:0]IM[3:0]
743 0
÷2
÷4
÷16
÷32
÷8
÷2
÷4
÷16
÷32
÷8
÷2
÷4
÷2
÷4
PLL1
÷4
I2C_SCL
÷2
N
I
2
C
Sampling
Clock
÷10
I
2
C
Master
SCL
I
2
C
Module
÷32
÷64
÷128
÷192
÷256
÷512
÷384
00000000
Ack
Sub-AddrAckSlave AddrS Ack
00000000
Ack
00000000
Ack
0xxxxxxx
Ack
IM1/OM1IM2/OM2IM3/OM3
XTALO
32 Bit
32 Bit
NOTE: F9 must not be updated without first muting all three monaural channels in the TAS3103.
See Section 2.1.1 for a detailed discussion of this restriction.
Serial Audio Port (AP) Mode Code
‡
‡
Input and output mode selections are independent.
†
Input and output word sizes are
independent.