Datasheet

1−18
GPIO and Watchdog Timer Subaddresses
SUBADDRESS(es) PARAMETER(s)
0xC8−0xC9 Factory Test Subaddresses
0xCA−0xCF SDIN4 Input Mixers
0xD0−0xD1 CH1/CH2 to CH3 After Effects Mixers
0xD2−0xEA Reserved
GPIO0
GPIO1
GPIO2 GPIO3
D
Q
D
Q
D
Q
D
Q
Sample
Logic
0xEF
Down Counter
LD
LRCLK
Decode 0
Watchdog
Counter
Reset
0xEB
PWRDN
DATA PATH SWITCH
Reset
GPIODIR
3
READ
EN
Determines How Many Consecutive Logic 0 Samples (Where Each Sample Is Spaced by GPIOFSCOUNT LRCLKs) Are Required to Read a Logic 0 on a GPIO Input Port
S Slave Addr Sub-AddrAck 00000000Ack
Ack
210
0000
Ack
GPIOFSCOUNT
Ack
GPIO_samp_int
Ack
31 24 23 20 19 16 15 8 7 0
S Slave Addr Sub-AddrAck 00000000Ack
Ack
31 24
00000000
23 16
Ack
00000000
15 8
Ack
0000000x
70
Ack
1 (Default State)
Disables Watchdog
Timer
Decode 2
16
Microprocessor Clock
Microprocessor
Microprocessor Firmware
Microprocessor Bus
Microprocessor Control
0xEE
GPIO_in_out
3
S Slave Addr Sub-AddrAck 00000000Ack
Ack
210
Ack
31 24 23 16 0
00000000
15 8
00000000
Ack
74
0000
Ack
3
I
2
C Slave Mode
and I
2
C Master Mode
Write I
2
C Master
Mode Read