Datasheet

4−4
4.4.2 Control Signals Over Recommended Operating Conditions (Unless Otherwise Noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
t
w1(L)
Pulse duration, RST low 10 ns
t
pd1
Propagation delay, PWRDN high to power down state asserted See Note 11 µs
t
pd2
Propagation delay, PWRDN low to power down state deasserted See Note 12 µs
NOTES: 11. The maximum worst case value for t
pd1
is given by
t
pd1_worst_case
+
4096 ) GPIOFSCOUNT
LRCLK
)
80
Microprocessor_Clock
12. t
pd2
is determined by the time it takes the internal digital PLL to reach a locked condition, which, in turn, is governed by the MCLKI/
XTALI frequency and the PLL output frequency. For a 135-MHz PLL output and an MCLKI value of 24.576 MHz, t
pd2
is typically 25 µs.
For an 11.264-MHz PLL output clock and a 1.024-MHz MCLKI/XTALI master clock, t
pd2
is typically 360 µs.
PWRDN
t
w1(L)
t
pd1
t
pd2
RST
Figure 4−2. Control Signals Timing Waveforms