Datasheet

3−55
Internal
Processing
Nodes
L
R
U
V
L
R
Time
LRCLK
SDOUT1
L
R
W
X
L
R
Time
LRCLK
SDOUT2
L
R
Y
Z
LR
Time
LRCLK
SDOUT3
SDOUT1
U
V
W
X
Y
Z
Node U
Nodes U & V
Nodes V & W
Nodes V, W & X
Nodes V, W, X & Y
Nodes V, W, Y & Z
Nodes W, X, Y & Z
Node X
(a) Discrete Mode − For I
2
S Format, Polarity of
LRCLK Opposite That Shown
(b) TDM Mode
Internal
Processing
Nodes
Internal
Processing
Nodes
Internal
Processing
Nodes
Figure 3−33. Processing Node to Serial Output Port Topology