Datasheet

1−3
1.3 Hardware Block Diagram
SDIN1
COEF
RAM
Data
RAM
Code
ROM
Data
Path
Memory
Interface
Delay
Memory
(4K x 16)
8051
MCU
Control
Registers
Volume
Update
4
I2C_SCL
I2C_SDA
CS1
CS0
GPIO[3:0]
8
54
48
28
SDIN2
SDIN4
SDIN3
SDOUT1
SDOUT2
SDOUT3
LRCLK
SCLKIN
MCLKO
SCLKOUT1
SCLKOUT2
76-Bit
ALU
Digital Audio Processor
Serial
Audio
Port
Controller
(8-Bit)
4
External
Data
RAM
Internal
Data
RAM
Code
ROM
8
2828
64
Oscillator
and
PLL
XTALI
XTALO
PWRDN
PLL0
PLL1
TEST
48
64
64
64
64
64
64
I
2
C
Serial
Interface
RST
I2CM_S