Datasheet

2−26
TAS3103A
RST
2 µF
10 kΩ
3.3 V
RST
SN74LVC1G07
26
Figure 2−22. External Power-Good Reset-Control Circuit
Note that RST
implements an asynchronous clear. This control can respond to narrow negative signal transitions.
Some applications, therefore, might require a high-frequency capacitor on the RST
pin to remove unwanted noise
excursions.
2.6 Power Down
Power down requires stable and accurate clocks during the transition from the operational state to the power-down
state, and during the transition for the power-down state to the operational state. If a clock error occurs during either
of these transitions, then the operation of the TAS3103A can be compromised and a reset may be required to restore
operation. Setting the PWRDN pin to logic 1 enables power down. Power down stops all clocks in the TAS3103A,
but preserves the state of the TAS3103A. When PWRDN is deactivated (set to logic 0) after a period of activation,
the TAS3103A resumes the processing of audio data on receiving the next LRCLK (indicating a new sample of audio
data is available for processing). The configuration of the TAS3103A and all programmable parameters are retained
during power down.
A time lag occurs between setting PWRDN to logic 1 and entering the power-down state. PWRDN is sampled every
GPIOFSCOUNT LRCLK periods (see subaddress 0xEF in Appendix A; Watchdog Timer, Section 2.7; and
General-Purpose I/O (GPIO) Ports; Section 2.8). This means that a time lag as great as GPIOFSCOUNT(1/LRCLK)
could exist between the activation of PWRDN (setting to logic 1) and the time at which the microprocessor recognizes
that the PWRDN pin has been activated. Normally, on recognizing that the PWRDN pin has been activated, the
TAS3103A enters the power-down state approximately 80 microprocessor clock cycles later. However, if a soft
volume update is in progress, the TAS3103A waits until the soft volume update is complete before entering the
power-down state. For this case then, the worst-case time lag between recognizing the activation of pin PWRDN and
entering the power-down state would be 4096 LRCLK periods, assuming a volume slew rate selection (bit VSC of
I
2
C subaddress 0xF1) of 4096 and the issuance of a volume update immediately preceding the reading of pin
PWRDN. The worst-case time lag between setting PWRDN to logic 1 and entering the power-down state is then:
power−down−time lag
Worst*Case
+
4096 ) GPIOFSCOUNT
LRCLK
)
80
Microprocessor * Clock
A time lag also between deactivating PWRDN (setting PWRDN to logic 0) and exiting the power-down state. This time
lag is set by the time it takes the internal digital PLL to stabilize, and this time, in turn, is set by the master clock
frequency (MCLKI or XTALI) and the PLL output clock frequency. For a 135-MHz PLL output clock and a 24.576
MCLKI, the time lag is approximately 25 µs. For an 11.264-MHz PLL output clock and a 1.024-MHz MCLKI, the time
lag is approximately 360 µs.
Power consumption in the power-down state is approximately 12 mW.
2.7 Watchdog Timer
A watchdog timer in the TAS3103A monitors the microprocessor activity. If the microprocessor ever ceases to execute
its stored program, the watchdog timer fires and resets the TAS3103A. This capability was included in the TAS3103A
for factory test purposes and has little use in applications. The program structure used in the microprocessor ensures
that the microprocessor always executes its stored program unless a hardware failure occurs.