Datasheet

2−24
S
S
S
S
S
S
47
40
39
32
31
24
23
22
21
20
19
16
15
8
7
0
Overhead/Guard Bits
16-Bit
Audio
18-Bit
Audio
20-Bit
Audio
24-Bit
Audio
Precision/Noise Bits
32-Bit
Audio
Figure 2−19. DAP Arithmetic Unit Data Word Structure
The arithmetic engine is a 48-bit (25.23-format) processor consisting of a general-purpose 76-bit arithmetic logic unit
(ALU) and function-specific arithmetic blocks. Multiply operations (excluding the function-specific arithmetic blocks)
always involve 48-bit DAP words and 28-bit coefficients (usually I
2
C programmable coefficients). If a group of
products is to be added together, the 76-bit product of each multiplication is applied to a 76-bit adder, where a DSP-like
multiply-accumulate (MAC) operation takes place. Biquad filter computations use the MAC operation to maintain
precision in the intermediate computational stages.
To maximize the linear range of the 76-bit ALU, saturation logic is not used. Intermediate overflows are then permitted
in multiply-accumulate operations, but it is assumed that subsequent terms in the multiply-accumulate computation
flow corrects the overflow condition. The biquad filter structure used in the TAS3103A is the direct form-I structure
and has only one accumulation node. With this type of structure, intermediate overflow is allowed as long as the
designer of the filters has ensured that the final output is bounded and does not overflow. Figure 2−20 shows a
bounded computation that experiences an intermediate overflow condition. For ease of illustration, 8-bit arithmetic
is used.
The DAP memory banks include a dual-port data RAM for storing intermediate results, a coefficient RAM, a 4K × 16
RAM for implementing the delay stages, and a fixed program ROM. Only the coefficient RAM, accessible via the I
2
C
bus, is available to the user.