Datasheet

2−22
2.3.2.2 I
2
C Slave Mode Operation
The I
2
C slave mode permits configuration parameters (other than volume via the GPIO pins for the I
2
C master mode)
to be changed. The TAS3103A can detect and reset the I
2
C interface when an invalid I
2
C command is received. This
feature is enabled by setting the I
2
C configuration control value N to zero. This feature is also enabled by the default
setting, 0x0000 0040, of the I
2
C configuration control register 0xFB. The I
2
C slave mode provides read access to the
spectrum analyzer and VU meter outputs. Configuration downloads from a master device can be used to replace the
I
2
C master mode EEPROM download.
For I
2
C read commands, the TAS3103A responds with data, a byte at a time, starting at the subaddress assigned,
as long as the master device continues to respond with acknowledges. If a given subaddress does not use all 32 bits,
the unused bits are read as logic 0. I
2
C write commands, however, are treated in accordance with the data assignment
for that address space. If a write command is received for a biquad subaddress, the TAS3103A expects to see five
32-bit words. If fewer than five data words have been received when a stop command (or another start command)
is received, the data received is discarded. If a write command is received for a mixer coefficient, the TAS3103A
expects to see only one 32-bit word.
Supplying a subaddress for each subaddress transaction is referred to as random I
2
C addressing. The TAS3103A
also supports sequential I
2
C addressing. For example, for write transactions, if a subaddress is issued followed by
data for that subaddress and the fifteen subaddresses that follow, a sequential I
2
C write transaction has taken place,
and the data for all 16 subaddresses is successfully received by the TAS3103A. For I
2
C sequential write transactions,
the subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop
or start is transmitted, determines how many subaddresses are written to. As was true for random addressing,
sequential addressing requires that a block of data be transmitted. If only a partial set of data is written to the last
subaddress, the data for the last subaddress is discarded. However, all other data written is accepted; just the
incomplete data is discarded.
The GPIO subaddresses require the downloading of four bytes of zero-valued spacer data in order to proceed to the
next subaddress. The TAS3103A can always receive sequential I
2
C addressing write data without issuing wait states.
Do not write to reserved and factory-test subaddresses.
The TAS3103A also supports sequential read transactions. When an I
2
C subaddress assignment write transaction
is followed by a read transaction, the TAS3103A outputs the data for that subaddress, and then continues to output
data for the subaddresses that follow as long as the master continues to issue data received acknowledges. With
only two exceptions, the TAS3103A outputs four bytes of zero-valued data for reserved and factory-test
subaddresses. The subaddresses of the exceptions and the number of bytes supplied by the TAS3103A for each
exception are given in Table 2−5. If a GPIO port is assigned as an output port, a logic 0 bit value is supplied by the
TAS3103A for this GPIO port in response to a read transaction at subaddress 0xEE.
CAUTION: Sequential write transactions must be in ascending subaddress order. The
TAS3103A does not wrap around from subaddress 0xFF to 0x00.
Sequential read transactions wrap around from subaddress 0xFF to 0x00.
Table 2−5. Four-Byte Read Exceptions—Reserved and Factory-Test I
2
C Subaddresses
SUBADDRESS NUMBER BYTES SUPPLIED BY TAS3103A
0xC9 8
0xED 8
NOTE: Table 2−5 does not include read-only subaddresses and thus does
not include subaddresses 0xFD, 0xFE, and 0xFF. When read, these
read-only subaddresses output 10, 2, and 1 byte, respectively.
Thus, for all reserved and factory-test subaddresses, except subaddresses 0xC9 and 0xED, the master device must
issue four data-received acknowledges for the four bytes of zero-valued data. For subaddresses 0xC9 and 0xED,
the master device must issue eight data-received acknowledges for the eight bytes of zero-valued data.
Sequential read transactions do not have restrictions on outputting only complete subaddress data sets. If the master
does not issue enough data-received acknowledges to receive all the data for a given subaddress, the master device