Datasheet

2−20
be included in the data written. There cannot be a separate write transaction to supply the subaddress, as was
required for read transactions. If a subaddress assignment only write transaction is followed by a second write
transaction supplying the data, erroneous behavior results. The first byte in the second write transaction is interpreted
by the TAS3103A as another subaddress replacing the one previously written.
S
Start
(By Master)
TAS3103A
Address
Acknowledge
(By TAS3103A)
7-Bit Slave
Address
(By Master)
W
Write
(By Master)
ACK Subaddress
TAS3103A
Subaddress
(By Master)
Acknowledge
(By TAS3103A)
ACK
S
Stop
(By Master)
S
Start
(By Master)
TAS3103A
Address
Acknowledge
(By TAS3103A)
7-Bit Slave
Address
(By Master)
R
Read
(By Master)
ACK Data
Data
(By TAS3103A)
ACK Data
Data
(By TAS3103A)
Acknowledge
(By Master)
ACK
Acknowledge
(By Master)
S
Stop
(By Master
)
NAK
No Acknowledge
(By Master)
S
Start
(By Master)
TAS3103A
Address
Acknowledge
(By TAS3103A)
7-Bit Slave
Address
(By Master)
W
Write
(By Master)
ACK Data
Data
(By Master)
ACK Data
Data
(By Master)
ACK S
Stop
(By Master)
ACKSubaddress
TAS3103A
Subaddress
(By Master)
Acknowledge
(By TAS3103A)
ACK
Acknowledge
(By TAS3103A)
Acknowledge
(By TAS3103A)
Acknowledge
(By TAS3103A)
I
2
C Write Transaction
I
2
C Read Transaction
Figure 2−17. I
2
C Subaddress Access Protocol
2.3.2.1 I
2
C Master Mode Operation
The TAS3103A uses the master mode to download an operational configuration. The I
2
C in master mode is only used
to download initialization parameters from EEPROM following reset or power down. The configuration downloaded
must contain data for all 256 subaddresses, with spacer data supplied for those subaddresses that are GPIO
subaddresses, read-only subaddresses, factory-test subaddresses, or unused (reserved) subaddresses. The spacer
data must always be assigned the value zero. Table 2−4 organizes the 256 subaddresses (and their corresponding
EEPROM addresses) into sequential blocks, with each block containing either valid data or spacer data.
Table 2−4 also illustrates that the subaddresses and their corresponding EEPROM memory addresses do not directly
correlate. This is because many subaddresses are assigned more than one 32-bit word. For example, there is a
unique subaddress for each biquad filter in the TAS3103A, but each subaddress is assigned five 32-bit
coefficients—resulting in 20 bytes of memory being assigned to each biquad subaddress.
The TAS3103A, in the I
2
C master mode, can execute a complete download without requiring any wait states. After
the TAS3103A has downloaded all 2367 bytes of coefficient and spacer data, the I
2
C bus is disabled and cannot be
used to update coefficient values or retrieve status or spectrum/VU meter data. Volume control is available in the
master mode via the four GPIO pins.
In I
2
C master mode, the watchdog timer must not be enabled.
When programming the EEPROM, make sure that the starting I
2
C check word (subaddress 0x00) and ending I
2
C
check word (subaddress 0xFC) are identical.