Datasheet

2−19
2.3.2 I
2
C Bus Controller
The TAS3103A has a bidirectional, two-wire, I
2
C-compatible interface. Both 100-kbps and 400-kbps data transfer
rates are supported, and the TAS3103A controller can serve as either a master I
2
C device or a slave I
2
C device.
Master/slave operation is defined by the logic level input into pin I2CM_S
(logic 1 = master mode, logic 0 = slave
mode).
If the voltage input level to I2CM_S
is changed, the TAS3103A must be reset.
In the I
2
C master mode, data rate transfer is fixed at 100 kHz, assuming MCLKI or XTALI = 12.288 MHz, PLL0 = PLL1
= 0, and MICROCLK_DIV = 0. In the I
2
C slave mode, data rate transfer is determined by the master device. However,
the setting of I
2
C parameter N at subaddress 0xFB (see DPLL and Clock Management, Section 2.2) does play a role
in setting the data transfer rate. In the I
2
C slave mode, bit rates other than (and including) the I
2
C-specific 100-kbps
and 400-kbps bit rates can be obtained, but N must always be set so that the oversample clock into the I
2
C
master/slave controller is at least a factor of 20 higher in frequency than SCL.
The I
2
C communication protocol for the I
2
C slave mode is shown in Figure 2−16.
I2C_SDA
I2C_SCL
C
S
1
†
S
Start
(By Master)
Slave Address
(By Master)
0
1 1 0 1
C
S
0
†
Read or Write
(By Master)
R
/
W
A
C
K
M
S
B
Acknowledge
(By TAS3103A)
L
S
B
Data Byte
(By Transmitter)
A
C
K
Acknowledge
(By Receiver)
M
S
B
L
S
B
Data Byte
(By Transmitter)
A
C
K
Acknowledge
(By Receiver)
S
Stop
(By Master)
MSB MSB−1 MSB−2 LSB
Start Condition
I2C_SDA ↓ While I2C_SCL = 1
Stop Condition
I2C_SDA ↑ While I2C_SCL = 1
†
Bits CS1 and CS0 in the TAS3103A slave address are compared to the logic levels on pins CS0 and CS1 for address verification. This provides
the ability to address up to four TAS3103A chips on the same I
2
C bus.
Figure 2−16. I
2
C Slave-Mode Communication Protocol
In the slave mode, the I
2
C bus is used to:
• Update coefficient values and output data to those GPIO ports configured as output.
• Read status flags, input data from those GPIO ports configured as inputs and retrieve spectrum
analyzer/VU meter data.
In the master mode, the I
2
C bus is used to download a user-specific configuration from an I
2
C compatible EEPROM.
In the slave mode only, specific registers and memory locations in the TAS3103A are accessible with the use of I
2
C
subaddresses. There are 256 such I
2
C subaddresses. The protocol required to access a specific subaddress is
presented in Figure 2−17.
As shown in Figure 2−17, a read transaction requires that the master device first issue a write transaction to give the
TAS3103A the subaddress to be used in the read transaction that follows. This subaddress assignment write
transaction is then followed by the read transaction. For write transactions, the subaddress is supplied in the first byte
of data written, and this byte is followed by the data to be written. For write transactions, the subaddress must always