Datasheet

2−18
When the SAP is in the master mode, it uses the MCLKI/XTALI master clock to drive the serial port clocks SCLKOUT1,
SLCKOUT2, and LRCLK. When the SAP is in the slave mode, LRCLK is an input and SCLKOUT2 and SCLKOUT1
are derived from SCLKIN. As shown in Figure 2−15, SCLKOUT1 clocks data into the input SAP and SCLKOUT2
clocks data from the output SAP. Two distinct clocks are required to support TDM-to-discrete and discrete-to-TDM
data format conversions. Such format conversions also require that SCLKIN be the higher valued bit clock frequency.
For TDM-in/discrete-out format conversions, SCLKIN must be equal to the input bit clock. For discrete-in/TDM-out
format conversions, SCLKIN must be equal to the output bit clock. The frequency settings for SCLKOUT1,
SCLKOUT2, and LRCLK in the SAP master mode, as well as the SAP master/slave mode selection, are all controlled
by I
2
C commands.
Table 2−3 lists the default settings at power turnon or after a received reset.
Table 2−3. TAS3103A Clock Default Settings
CLOCK DEFAULT SETTING
SCLKOUT1 SCLKIN
SCLKOUT2 SCLKIN
LRCLK Input
MCLKO MCLKI or XTALI
DAP processing clock Set by pins PLL0 and PLL1
Microprocessor clock Set by pin MICROCLK_DIV
I
2
C sampling clock I
2
C master mode
Microprocessor clock/4
I
2
C slave mode
Microprocessor clock
I
2
C master SCL I
2
C sampling clock/90
The selections provided by the dedicated TAS3103A input pins and the programmable settings provided by I
2
C
subaddress commands give the TAS3103A a wealth of clocking options. Table 2−1, in the section describing the SAP,
lists typical clocking selections for different audio sampling rates. However, the following clocking restrictions must
be adhered to:
• MCLKI or XTALI ≥ 128 Fs (NOTE: For some TDM modes, MCLKI or XTALI must be ≥ 256
Fs)
• DAP clock ≥ 1400 × Fs
• DAP clock < 136 MHz
• Microprocessor clock/20 ≥ I
2
C SCL clock
• Microprocessor clock ≤ 35 MHz
• XTALI ≤ 20 MHz
• MCLKI ≤ 25 MHz, unless PLL is bypassed
As long as these restrictions are met, all other clocking options are allowed.
2.3 Controller
The controller serves as the interface between the DAP, the asynchronous I
2
C bus interface, and the four
general-purpose I/O (GPIO) pins. Included in the controller block is an industry-standard 8051 microprocessor and
an I
2
C master/slave bus controller.
2.3.1 8051 Microprocessor
The 8051 microprocessor receives and distributes I
2
C write data, retrieves and outputs to the I
2
C bus controller the
required I
2
C read data, and participates in most processing tasks requiring multiframe processing cycles. The
microprocessor also controls the flow of data into and out of the GPIO pins, which includes volume control when in
the I
2
C master mode. The microprocessor has its own data RAM for storing intermediate values and queuing I
2
C
commands, and a fixed program ROM. The microprocessor program cannot be altered.