Datasheet

2−17
2.2.2 The Microprocessor Clock and I
2
C
The selected microprocessor clock is also used to drive the clocks used by the I
2
C control block. Two parameters,
N and M, define the clocks used by the I
2
C control block. The I
2
C control block sampling frequency is set by 1/2
N
,
where N can range in value from 0 to 7. A 1/(1 + M) divisor followed by a 1/10 divisor generates the data bit clock
(SCL). This derived SCL clock is only used when the I
2
C control block is set to master mode (input pin I2CM_S = 1).
The default value for the I
2
C parameter N depends on whether the I
2
C controller is in slave mode (I2CM_S = 0) or
master mode (I2CM_S
= 1). In the I
2
C master mode, N = 2 (2
N
= 4), which ensures that a 100-kHz I
2
C data clock
(SCL) can be generated when the digital audio processor (DAP) is running at its maximum frequency of 135 MHz.
In the I
2
C slave mode, N = 0 (2
N
= 1), which ensures the I
2
C controller an adequate oversampling clock when the
DAP is running at the minimum clock frequency required to process 8-kHz audio data (approximately 11.2 MHz). In
I
2
C master mode, the values for M and N are fixed and cannot be changed.
SCLKIN
OSC
PLL and Clock Management
I2C_SDA
Digital Audio Processor
(DAP)
MCLKO PLL1 PLL0 SCLKOUT1 LRCLK MICROCLK_DIV SCLKOUT2
I2C_SCL
8-Bit
WARP
8051 Microprocessor
1/2
N
1/(M+1)
I
2
C
Master/Slave
Controller
÷10
Master
SCL
MCLKI XTALI XTALO
M
U
X
÷Y = 64
DEFAULT
M
U
X
M
U
X
÷2
÷2
M
U
X
MCLK
PLL
(x11)
M
U
X
÷2
÷2
M
U
X
÷4
M
U
X
Input
SAP
Microprocessor
and
I
2
C Bus Controller
Output
SAP
N = 0 (I
2
C Slave Default)
= 2 (I
2
C Master Default)
I2CM_S
÷ X = 1
DEFAULT
÷ Z = 2
DEFAULT
Oversample Clock
Figure 2−15. DPLL and Clock Management Block Diagram