Datasheet

2−14

2.2 DPLL and Clock Management

Clock management for the TAS3103A consists of two control structures:

• Master clock management: oversees the selection of the clock frequencies for the microprocessor, the I

controller, and the digital audio processor (DAP). The master clock (MCLKI or XTALI) serves as the source

for these clocks. In most applications, the master clock is input to an on-chip digital phase-locked loop

(DPLL), and the DPLL output is used to drive the microprocessor and DAP clocks. A DPLL bypass mode

can also be used, in which case the master clock is used to drive the microprocessor and DAP clocks.

• Serial audio port (SAP) clock management: oversees SAP master/slave mode, the settings of SCLKOUT1

and SCLKOUT2, and the setting of LRCLK in the SAP master mode.

Figure 2−15 illustrates the clock circuitry in the TAS3103A. The bold lines in Figure 2−15 highlight the default settings

at power turnon, or after a reset. Inputs MCLKI and XTALI source the master clock for the TAS3103A. Within the

TAS3103A, these two inputs are combined by an OR gate, and thus only one of these two sources can be active at

any one time. The source that is not active must be set to logic 0. In normal operation, the master clock is divided

by 1, 2, or 4 as determined by the logic levels set at input pins PLL0 and PLL1 (the state of PLL0, PLL1, and

MICROCLK_DIV should only be changed while the TAS3103A RST

is held LOW) and then multiplied by 11 in

frequency by the on-chip DPLL. The DPLL output (or MCLKI/XTALI if the DPLL is bypassed) is the processing clock

used by the digital audio processor (DAP).

The DAP processing clock can also serve as the clock for the on-chip microprocessor, or the DAP clock can be divided

by four prior to sending it to the microprocessor. The input pin MICROCLK_DIV makes this clock choice. A logic 1

input level on this pin selects the DAP clock for the microprocessor clock; a logic 0 input level on this pin selects the

DAP clock/4 for the microprocessor clock. Table 2−2 lists the primary clock modes of the TAS3103A.