Datasheet

2−10
TAS3103A
TAS3103A
U1
ORIN
SDOUT1
U2
ORIN
SDOUT1
(AB = 1)
(AB = 0)
LR
U
U2
LRCLK
SDOUT1
U1
32 32 32 32 32 32 32 32
LR
U
LRCLK
U2 V W X
32 32 32 32 32 32 32 32
U1 U V W 0 X
32 32 32 32 32 32 32 32
U
U1
V
U2
W
U2
X
U2
V
U1
W
U1
X
U1
SCLKs
SCLKs
SCLKs
Figure 2−10. 8-CH TDM Format Using SAP Modes 0101 and 1000
TAS3103A
TAS3103A
U1
ORIN
SDOUT1
U2
ORIN
SDOUT1
(AB = 0)
(AB = 1)
LR
U
U1
LRCLK
SDOUT1
U1
32 32 32 32 32 32 32 32
LR
U
LRCLK
U1 V W 0
32 32 32 32 32 32 32 32
U2 U 0 W Y 0
32 32 32 32 32 32 32 32
U
U2
V
U1
W
U1
Y
U2
W
U2
SCLKs
SCLKs
SCLKs
Figure 2−11. 6-CH Data, 8-CH Transfer TDM Format Using SAP Modes 0101 and 1000
For these same two modes, if register X in chip AB = 0 is set to zero, and registers V and X in chip AB = 1 are set
to zero, the resulting format is a 6-CH data, 8-CH transfer format. This option is shown in Figure 2−11.
The data output format in Figure 2−11 is identical to that realized using data output formats 1100 and 1110 in
Figure 2−7. The difference is that SAP modes 1010 and 1000 provide six independent monaural channels to process
the data, whereas SAP modes 1100 and 1110 provide only three independent monaural channels to process the data.
2.1.2 Processing Flow—SAP Input to SAP Output
All SAP data format options other than I
2
S result in a two-sample delay from input to output, as illustrated in
Figure 2−12. Figure 2−12 is also relevant if I
2
S formatting is used for both the input SAP and the output SAP (the
polarity of LRCLK in Figure 2−12 must be inverted in this case). However, if I
2
S format conversions are performed
between input and output, the delay becomes either 1.5 samples or 2.5 samples, depending on the processing clock
frequency selected for the digital audio processor (DAP) relative to the sample rate of the incoming data. The
input-to-output delay for an I
2
S input format and a non-I
2
S output format is illustrated in Figure 2−13(a), and
Figure 2−13(b) illustrates the delay for a non-I
2
S input format and an I
2
S output format. In each case, two distinct
input-to-output delay times are shown: a 1.5-sample delay time if the processing time in the DAP is less than half the
sample period, and a 2.5-sample delay time if the processing time in the DAP is greater than half the sample period.
The departure from the two-sample input-to-output processing delay when I
2
S format conversions are performed is
due to the use of a common LRCLK. The I
2
S format uses the falling edge of LRCLK to begin a sample period, whereas
all other formats use the rising edge of LRCLK to begin a sample period. This means that the input SAP and digital
audio processor (DAP) operate on sample windows that are 180° out of phase with respect to the sample window
used by the output SAP. This phase difference results in the output SAP outputting a new data sample at the midpoint
of the sample period used by the DAP to process the data. If the processing cycle completes all processing tasks
before the midpoint of the processing sample period, the output SAP outputs this processed data. However, if the
processing time extends past the midpoint of the processing sample period, the output SAP outputs the data
processed during the previous processing sample period. In the former case, the delay from input to output is 1.5
samples. In the latter case, the delay from input to output is 2.5 samples.