Datasheet

2−2
76-Bit Adder
Regs
Regs
32 Bits
32 Bits
32 Bits
32 Bits
SDIN1
32 Bits
SDIN2
32 Bits
SDIN3
32 Bits
SDIN4
INPUT SAP
256 Bits
64 Bits
OUTPUT SAP
SDOUT
3
SDOUT
2
SDOUT
1
SCLKIN
OSC
PLL and Clock Management
ORIN
I2C_SDA
GPIO0
Controller
Arithmetic
Engine
Dual Port
Data RAM
Coefficient
RAM
4K × 16
Delay Line
RAM
Program
ROM
DAP
Instruction Decoder/Sequencer
Digital Audio Processor
(DAP)
Arithmetic Unit
MCLKO PLL1 PLL0 SCLKOUT1 LRCLK MICROCLK_DIV SCLKOUT2
CS0 CS1I2C_SCL GPIO1 GPIO2 GPIO3
Volume
Update
2K × 8
Data
RAM
16K × 8
Program
ROM
256 × 8
Data
RAM
8-Bit
WARP
8051 Microprocessor
1/2
N
Reg
1/(M+1)
I
2
C
Master/Slave
Controller
÷10
Master
SCL
Reg
64 Bits
MCLKI XTALI XTALO
M
U
X
÷Y
÷X
M
U
X
÷Z
M
U
X
÷2
÷2
M
U
X
MCLK
PLL
(x11)
M
U
X
÷2
÷2
M
U
X
÷4
M
U
X
I2CM_S
Oversample Clock
Figure 2−1. TAS3103A Detailed Hardware Block Diagram