Datasheet

1−22
6-CH, single-chip, crystal (I
2
S)
6-CH, single-chip (LJ)
6-CH, single-chip, crystal (LJ)
Discrete, 16-bit packed
Word Size Code
†
DIGITAL AUDIO FORMAT AND CLOCK MANAGEMENT
OSC
XTALI
0 1 2 3
MCLKO
0 1 2
PLL0
x11 PLL
MUX
MUX
PLL BYPASS
Digital Audio
Processor
Clock
PLL[1:0]
0 1 2 3 4 5 6 7
MUX
MUX
CRYSTAL
0 1 2 3
MUX
1 0
MUX
0 1 2 3 4 5 6 7
MUX
0 1 2 3 4 5 6 7
MUX
1 0
MUX
0 1
SCLKIN
SCLKOUT2 SCLKOUT1
LRCLK
0xF9
DWFMT (Data Word Format)
Word Size
32-bit
16-bit (default)
18-bit 20-bit 24-bit 32-bit
IM0/OM0
0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
Mode
Discrete, left-justified
Discrete, left-justified (default)
Discrete, right-justified
TDM_LJ_8
TDM_LJ_6
TDM_LJ_4
TDM_I2S_8 TDM_I2S_6
TDM_I2S_4
TDM_20Bit_6
AB assigns TDM time slots for those TDM outputs involving two TAS3103As. For these output formats, one of the TAS3103A chips must be defined as AB = 0. The other TAS3103A chip must be defined as AB = 1.
MCLKI
IW2/OW2
0 0 0 0 1 1 1 1
IW1/OW1
0 0 1 1 0 0 1 1
IW0/OW0
0 1 0 1 0 1 0 1
AckIOMAck
OW[2:0]
15
IW[2:0]
0
AB
14 13 11 10 8
7
DWFMT
815
Ack
z[2:0]IMS x[2:0]ICS
§
Ack x[2:0]y[2:0]w[1:0]000AckSubaddrAckSlave AddrS
161819212223242627282931
OM[3:0]IM[3:0]
743 0
÷2
÷4
÷16
÷32
÷8
÷2
÷4
÷16
÷32
÷8
÷2
÷4
÷2
÷4
PLL1
÷32
÷64
÷128 ÷192 ÷256 ÷512 ÷384
IM1/OM1IM2/OM2IM3/OM3
XTALO
32-bit 32-bit
NOTE: See Section 2.1.1 for a detailed discussion of restrictions regarding updating of the 0xF9 register.
Serial Audio Port (AP) Mode Code
‡
‡
Input and output mode selections are independent.
†
Input and output word sizes are independent.
I
2
C Block
§
I
2
S MASTER/SLAVE
bit
Discrete, I
2
S
6-CH, single-chip, 20-bit