Datasheet

1−9
1.7 Operational Modes
The TAS3103A operation is governed by I/O terminal voltage level settings and register/coefficient settings within the
TAS3103A. The terminal settings are wholly sufficient to address all external environments, allowing the remaining
configuration settings to be determined by either I
2
C commands or by the content of an I
2
C serial EEPROM (when
the I
2
C master mode is selected).
1.7.1 Terminal-Controlled Modes
1.7.1.1 Clock Control
PLL1 PLL0 DAP CLOCK
0 0 11 × MCLK
0 1 (11 × MCLK)/2 (default)
1 0 (11 × MCLK)/4
1 1 MCLK (PLL bypass)
MICROCLK_DIV MICROPROCESSOR CLOCK
0 DAP clock/4 (default)
1 DAP clock
XTALIMCLKI
Reference
Divider
PLL
PLL0
Digital
Audio Processor
(DAP) Clock
MICROCLK_DIV
MCLK
PLL1
÷ 11
Microprocessor
Clock < 36 MHz
Microprocessor
Scaler
1400 y Fs 3 DAP Clock 3 136 MHz
y 11
1.7.1.2 I
2
C Bus Setup
SLAVE ADDRESS CS1 CS0
0x68/69 (default) 0 0
0x6A/6B 0 1
0x6C/6D 1 0
0x6E/6F 1 1
I2CM_S I
2
C BUS MODE
0 Slave
1 Master (default)—EEPROM device ID = 0xA0