Datasheet

1−7
TERMINAL
PULLUP/
DOWN
(2)
DESCRIPTION
NAME
PULLUP/
DOWN
(2)
DESCRIPTION
TYPE
(1)
I/ONO.
PWRDN 2 I D PWRDN powers down all logic and stops all clocks whenever logic high is
applied. However, the coefficient memory remains stable through a
power-down cycle, as long as a reset is not sent after a power-down cycle.
Pulldown
REGULATOR_EN 3 I D REGULATOR_EN is only used in factory tests. This pin should always be tied
to ground.
None
RST 26 I D RST is the master reset input. Applying a logic low to this pin generates a
master reset. The master reset results in all coefficients being set to their
power-up default state, all data memories being cleared, and all logic signals
being returned to their default values.
Pullup
SCLKIN 1 I D SCLKIN is the serial audio port (SAP) input data clock. This clock is only used
when the SAP is a slave. In master mode, SCLKOUT1 internally provides the
serial input clock (SCLKOUT1 from a given TAS3103A must not be connected
to SCLKIN on the same TAS3103A chip).
Pulldown
SCLKOUT1 35 O D SCLKOUT1 is one of two serial output bit clocks. It is divided from
MCLKI/XTALI in master mode, and SCLKIN in slave mode. Subaddress
control fields determine the divide ratio in both cases. When the serial audio
port is in master mode, SCLKOUT1 is used to receive incoming serial data and
should be wired to the data source(s) providing data to the SDIN inputs.
None
SCLKOUT2 36 O D SCLKOUT2 is one of two serial output bit clocks. It is divided from
MCLKI/XTALI in master mode, and SCLKIN in slave mode. Subaddress
control fields determine the divide ratio in both cases. SCLKOUT2 is always
used to clock out serial data from the three serial SDOUT output data
channels. SCLKOUT2 is provided separately from SCLKOUT1 to allow
discrete-in to TDM-out and TDM-in to discrete-out data format conversions
without the use of external glue logic.
Output
SDIN1 14 I D SDIN1, SDIN2, SDIN3, and SDIN4 are the four TAS3103A serial data input
ports. All four input ports support four discrete (stereo) data formats. SDIN1 is
the only data input port that also supports 11 time division multiplexed data
formats. All four ports are capable of receiving data with bit rates up to 24.576
MHz.
Pulldown
SDIN2 15 I D SDIN2 is one of the four TAS3103A serial data input ports. SDIN2 supports
four discrete (stereo) data formats, and is capable of receiving data with bit
rates up to 24.576 MHz.
Pulldown
SDIN3 16 I D SDIN3 is one of the four TAS3103A serial data input ports. SDIN4 supports
four discrete (stereo) data formats, and is capable of receiving data with bit
rates up to 24.576 MHz.
Pulldown
SDIN4 17 I D SDIN4 is one of the four TAS3103A serial data input ports. SDIN4 supports
four discrete (stereo) data formats, and is capable of receiving data with bit
rates up to 24.576 MHz.
Pulldown
SDOUT1 30 O D SDOUT1, SDOUT2, and SDOUT3 are the three TAS3103A serial data output
ports. All three output ports support four discrete (stereo) data formats.
SDOUT1 is the only data output port that also supports 11 time division
multiplexed data formats. All three ports are capable of outputting data at bit
rates up to 24.576 MHz.
None
SDOUT2 32 O D SDOUT2 is one of the three serial data output ports. SDOUT2 supports four
discrete (stereo) data formats, and is capable of outputting data at bit rates up
to 24.576 MHz.
None
SDOUT3 33 O D SDOUT3 is one of the three serial data output ports. SDOUT3 supports four
discrete (stereo) data formats, and is capable of outputting data at bit rates up
to 24.576 MHz.
None
TEST 10 I D TEST is only used in factory tests. This pin must be left unconnected or
grounded.
Pulldown