Datasheet

1−5
1.5 Ordering Information
T
A
PLASTIC
38-PIN TSSOP
(DBT)
0°C to 70°C TAS3103ADBT
1.6 Terminal Functions
TERMINAL
DESCRIPTION
PULLUP/
(2)
NAME NO. I/O TYPE
(1)
DESCRIPTION
PULLUP/
DOWN
(2)
A_VDDS (3.3 V) 7 PWR The PWR pin is used to input 3.3-V power to the DPLL and clock oscillator.
This pin can be connected to the same power source used to drive the DVSS
power pin. To achieve low DPLL jitter, this pin should be bypassed to AVSS
with a 0.47-µF capacitor (low-ESR preferable).
None
AVDD_BYPASS_CAP 6 PWR AVDD_BYPASS_CAP is a pinout of the internally regulated 1.8-VDC power
used by the DPLL and crystal oscillator. This pin should be connected to pin 8
with a 0.47-µF capacitor (low-ESR preferable). This pin must not be used to
power external devices.
None
AVSS 8 PWR AVSS is the ground reference for the internal DPLL and oscillator circuitry.
This pin needs to reference the same ground as DVSS power pin. To achieve
low DPLL jitter, ground noise at this pin must be minimized. The availability of
the AVSS pin allows a designer to use optimizing techniques such as star
ground connections, separate ground planes, or other quiet ground
distribution techniques to achieve a quiet ground reference at this pin.
None
CS0 24 I D CS0 is the LSB of a 2-bit code used to generate part of an I
2
C device address
that makes it possible to address four TAS3103A ICs on the same bus without
additional chip select logic. The pulldowns on the inputs select 00 as a default
when neither CS0 nor CS1 is connected.
Pulldown
CS1 25 I D CS1 is the MSB of a 2-bit code used to generate part of an I
2
C device address
that makes it possible to address four TAS3103A ICs on the same bus without
additional chip select logic.
Pulldown
DVDD_BYPASS_CAP 29 PWR DVDD_BYPASS_CAP is a pinout of the internally regulated 1.8-V power used
by all internal digital logic. This pin must not be used to power external devices.
A ceramic capacitor of at least 4.7 µF should be placed as close to the device
as possible between this pin and pin 28. A 0.01 µF should be connected in
parallel for high-frequency decoupling.
None
DVSS 28 PWR DVSS is the digital ground pin. None
GPIO0 18 I/O D GPIO0 is a general-purpose I/O, controlled by the internal microprocessor
through I
2
C commands. When in the I
2
C master mode, GPIO0 serves as a
volume-up command for CH1/CH2.
Pullup
GPIO1 19 I/O D GPIO1 is a general-purpose I/O, controlled by the internal microprocessor
through I
2
C commands. When in the I
2
C master mode, GPIO1 serves as a
volume-down command for CH1/CH2.
Pullup
GPIO2 20 I/O D GPIO2 is a general-purpose I/O, controlled by the internal microprocessor
through I
2
C commands. When in the I
2
C master mode, GPIO2 serves as a
volume-up command for CH3.
Pullup
GPIO3 21 I/O D GPIO3 is a general-purpose I/O, controlled by the internal microprocessor
through I
2
C commands. When in the I
2
C master mode, GPIO3 serves as a
volume-down command for CH3.
Pullup
I2CM_S 27 I D I2CM_S is a non-latched input that determines whether the TAS3103A acts as
an I
2
C master or slave. Logic high, or no connection, sets the TAS3103A as an
I
2
C master device. A logic low sets the TAS3103A as an I
2
C slave device. As a
master I
2
C device, the TAS3103A I
2
C port must have access to an external
EEPROM for input.
Pullup