Datasheet

4−7
4.4.5 Characteristics of the SDA and SCL I/O Stages for F/S-Mode I
2
C-Bus Devices
PARAMETER
TEST
STANDARD MODE FAST MODE
UNITS
PARAMETER
TEST
CONDITIONS
MIN MAX MIN MAX
UNITS
V
IL
LOW-level input voltage –0.5 0.3 V
DD
–0.5 0.3 V
DD
V
V
IH
HIGH-level input voltage 0.7 V
DD
0.7 V
DD
V
V
hys
Hysteresis of inputs N/A N/A 0.05 V
DD
V
V
OL1
LOW level output voltage (open drain or
open collector)
3 mA sink current 0 0.4 V
t
of
Output fall time from V
IHmin
to V
ILmax
Bus capacitance
from 10 pF to
400 pF
250
7 + 0.1 C
b
(2)
250 ns
I
i
Input current, each I/O pin –10 10 –10
(3)
10
(3)
µΑ
t
SP
Pulse width of spikes which must be
suppressed by the input filter
N/A N/A 0 0
(1)
ns
C
i
Capacitance, each I/O pin 10 10 pF
NOTES: 1. SCL and SDA do not have a 50-ns glitch filter.
NOTES: 2. C
b
= capacitance of one bus line in pF. The output fall time is faster than the standard I
2
C specification.
NOTES: 3. The I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if V
DD
is switched off.
Caution: The TAS3103A does not have 50-ns glitch filtering on the SCL and SDA inputs.
Caution: SDA does not have the standard I2C specification 300-ns internal hold time. SDA must be valid by the rising
and falling edges of SCL.