Datasheet

1−4
1.4 Functional Block Diagram
Cross-
bar
Mixer
Multi-
Mode
3D
Effects
Block
Multi-
Mode
Serial
to
PCM Input
Port
SDIN1 SDIN2 SDIN3
DRC
Center
Output
Cross-
bar
Multi-
plexer
Multi-
mode
PCM
to
Serial
Output
Port
PLL
and
Dividers
Oscillator
3 Mono Processing Channels
GPIO[3:0] CS0 CS1PLL1
VDDS DVSS
XTALI
TEST
PWRDN
LRCLK SCLKIN SCLKOUT1 SCLKOUT2 MCLKO
DVDD_ BYPASS_
SDIN4
Input
Treble
and
Soft
Volume
Loudness
Compensation
Ganged
DRC
Delay
Programmable
Dither
CH1
MCLKI
CH1
Microprocessor
PLL0
MICROCLK
Voltage Regulation
XTALO
or
Spectrum Analyzer
Bass
12
Biquad
Filters
CH2 CH3
Treble
and
Soft
Volume
Loudness
Compensation
Bass
12
Biquad
Filters
Treble
and
Soft
Volume
Loudness
Compensation
Bass
12
Biquad
Filters
VU Meter
Delay Delay
SDOUT1 SDOUT2 SDOUT3 ORIN
Programmable
Dither
Programmable
Dither
CH2 CH3
I2C_
SDA
I2C_
SCL
I2CM_S
CAP
AVSS A_VDDS
AVDD_ BYPASS_
CAP
I
2
S Clock Input/Generation
RST
_DIV