Data Manual January 2006 Digital Audio Solutions SLES166
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Contents Section 1 2 3 Title Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1 1.2 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2 1.3 Hardware Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3 1.
3.6 4 iv Soft Volume/Loudness Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−18 3.6.1 Soft Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−18 3.6.2 Loudness Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−25 3.6.3 Time Alignment and Reverb Delay Processing . . . . . . . . . . 3−27 3.7 Dynamic Range Control (DRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−30 3.7.1 DRC Implementation . . . . . . .
List of Illustrations Figure Title Page 2−1 TAS3103A Detailed Hardware Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 2−2 2−2 Discrete Serial Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3 2−3 Four-Channel TDM Serial Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3 2−4 SAP Configuration Subaddress Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 Input Mixer Topology—Internal Processing Nodes G and H . . . . . . . . . . . . . . 3−7 3−10 TAS3103A 3D Effects Processing Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9 3−11 Biquad Filter Structure and Coefficient Subaddress Format . . . . . . . . . . . . 3−10 3−12 Tone Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−12 3−13 Bass and Treble Filter Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table Title 2−1 TAS3103A Throughput Latencies vs MCLK and LRCLK . . . . . . . . . . . . . . . . 2–2 Sample Rate and CLK Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3 TAS3103A Clock Default Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4 I2C EEPROM Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
1 Introduction The TAS3103A is a fully configurable digital audio processor that preserves high-quality audio by using a 48-bit data path, 28-bit filter coefficients, a single-cycle 28 × 48-bit multiplier and a 76-bit accumulator. Because of the coefficient-configurable fixed-program architecture of the TAS3103A, a complete set of user-specific audio processing functions can be realized, with short development times, in a small, low-power, low-cost device.
1.2 Terminal Assignments DBT PACKAGE (TOP VIEW) SCLKIN PWRDN REGULATOR_EN XTALI (1.8-V logic) XTALO (1.8-V logic) AVDD_BYPASS_CAP A_VDDS (3.3 V) AVSS MCLKI TEST MICROCLK_DIV I2C_SDA I2C_SCL SDIN1 SDIN2 SDIN3 SDIN4 GPIO0 GPIO1 1−2 1 38 2 37 3 36 4 35 5 34 6 33 7 32 8 31 9 30 10 29 11 28 12 27 13 26 14 25 15 24 16 23 17 22 18 21 19 20 LRCLK ORIN SCLKOUT2 SCLKOUT1 MCLKO SDOUT3 SDOUT2 VDDS (3.
1.
1−4 SDIN4 SDIN3 SDIN2 SDIN1 XTALO MCLKI XTALI MultiMode Serial to PCM Input Port Input Crossbar Mixer Oscillator PLL0 MultiMode 3D Effects Block PLL and Dividers CH3 CH2 CH1 I2C_ SDA PLL1 MICROCLK _DIV 1.
1.5 Ordering Information TA PLASTIC 38-PIN TSSOP (DBT) 0°C to 70°C TAS3103ADBT 1.6 Terminal Functions TERMINAL NAME NO. I/O TYPE(1) DESCRIPTION PULLUP/ DOWN(2) A_VDDS (3.3 V) 7 PWR The PWR pin is used to input 3.3-V power to the DPLL and clock oscillator. This pin can be connected to the same power source used to drive the DVSS power pin. To achieve low DPLL jitter, this pin should be bypassed to AVSS with a 0.47-µF capacitor (low-ESR preferable).
TERMINAL PULLUP/ DOWN(2) NO. I/O TYPE(1) DESCRIPTION I2C_SCL 13 I/O D I2C_SCL is the I2C clock pin. When the TAS3103A I2C port is a master, I2C_SCL is (1/2N) × (1/(M+1)) × 1/10 times the microprocessor clock, where N and M are set to 2 and 8, respectively. When the TAS3103A I2C port is a slave, input clock rates up to 400 kHz can be supported. This pin must be provided an external pullup (2 kΩ is recommended for most applications).
TERMINAL PULLUP/ DOWN(2) NO. I/O TYPE(1) DESCRIPTION PWRDN 2 I D PWRDN powers down all logic and stops all clocks whenever logic high is applied. However, the coefficient memory remains stable through a power-down cycle, as long as a reset is not sent after a power-down cycle. Pulldown REGULATOR_EN 3 I D REGULATOR_EN is only used in factory tests. This pin should always be tied to ground. None RST 26 I D RST is the master reset input.
TERMINAL PULLUP/ DOWN(2) NO. I/O TYPE(1) DESCRIPTION VDDS (3.3 V) 31 - PWR VDDS is the 3.3-V pin that powers (1) the 1.8-V internal power regulator used to supply logic power to the chip and (2) the I/O ring. It is recommended that this pin be bypassed to DVSS (pin 28) with a low-ESR capacitor of 47 µF or greater. A 0.1-µf ceramic capacitor should be placed in parallel with the 47-µf capacitor to provide high-frequency decoupling. None XTALI (1.
1.7 Operational Modes The TAS3103A operation is governed by I/O terminal voltage level settings and register/coefficient settings within the TAS3103A. The terminal settings are wholly sufficient to address all external environments, allowing the remaining configuration settings to be determined by either I2C commands or by the content of an I2C serial EEPROM (when the I2C master mode is selected). 1.7.1 Terminal-Controlled Modes 1.7.1.
TAS3103A I2C Slave Address ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎ SDA a6 = 0 a5 = 1 a4 = 1 a3 = 0 a2 = 1 a1=CS1 a0=CS0 SCL 1 2 3 4 5 6 7 Start 1.7.1.
1−11 Slave Addr S Slave Addr Slave Addr S Slave Addr Ack Ack Ack Ack Ack m s xxxxxxx b Ack xxxxxxxx Ack m Ack 0000 s xxx b Ack xxxxxxxx Ack xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx Ack Ack Ack Ack xxxxxxxx xxxxxxxx Ack Ack Ack Ack xxxxxxxx xxxxxxxx 0x4E CH3 m Ack 0000 s xxx b m 0000 s xxx b 0x4D CH2 Subaddr 0x4C xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx CH1 Ack Ack Ack Ack Ack Subaddress Reverb Block Gains xxxxxxxx Ack Reverb Block Subaddr m A
1−12 S Ack Slave Addr Slave Addr S xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx Ack Ack Ack Ack Ack Ack Ack Ack Ack m Ack 0000 s xxx b m 0000 s xxx b xxxxxxxx xxxxxxxx Ack Ack CH3 = 0x75 CH2 = 0x74 CH1 = 0x73 Ack Ack xxxxxxxx l s b l s b l s b l s b l s b b0 b1 Ack Ack b2 a2 Ack Ack a1 Ack Ack Inline Gain Ack Bypass Gain Ack xxxxxx Ack xxxxxx Ack xxxxxx Ack xxxxxx Ack xxxxxx l Ack xxxxxx s b l Ack xxxxxx s b xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx B
1−13 CH3 CH2 Ack Subaddr 0x7B = Mix n to m 0x78 = Mix w to m 0x7A = Mix l to k 0x77 = Mix v to k 0x79 = Mix j to i 0x76 = Mix u to i Slave Addr CH1 S Ack xxxxxxxx CH3 Bass and Treble Block Mix_w_to_m CH2 Bass and Treble Block Σ w Σ CH3 Soft Volume j Σ l Mix_l_to_k Σ n Mix_n_to_m Subaddr Σ o DRC_bypass_3 Σ q Mix_n_to_q_via_DRC_mult DRC_bypass_2 Σ p Mix_l_to_p_via_DRC_mult CH3 CH2 CH1 m Ack 0000 s xxx b m 0000 s xxx b Mix_j_to_o_via_DRC_mult DRC_bypass_1 S Slave
1−14 Subaddr m Ack 0000 s xxx b Ack xxxxxxxx Ack xxxxxxxx Subaddr m Ack 0000 s xxx b Ack xxxxxxxx Ack xxxxxxxx Ack Ack l Ack xxxxxx s b l Ack xxxxxx s b CH3 to CH1 and CH2 Mix Gain Coefficients Ack 0x82 = Mix CH3 Output to o − 28-Bit Coefficient 0x83 = Mix CH3 Output to p − 28-Bit Coefficient Slave Addr CH1 CH2 S Ack 0x7F = Mix Dither 1 to o − 28-Bit Coefficient 0x80 = Mix Dither 2 to p − 28-Bit Coefficient 0x81 = Mix Dither 3 to q − 28-Bit Coefficient Slave Addr CH1 CH2 CH3 S Dith
1−15 Volume Commands I2C Bus Slave Addr Ack Subaddr Ack 0xF2 CH1 S S xxxxxxxx Ack xxxxxxxx CCC Ack xxxxxxxx Ack xxxxx HHH Ack 321 Ack Ack xxxxxxxx l Ack xxxxxxx s Ack b ttransition Commanded Volume 48 AUDIO IN = x16 BoostMAX Volume Command = 1/223 Cut MAX (LSB) (5.
1−16 Audio Input CH2 Audio Input CH1 or CH3 5.23 Format RMS Voltage Estimator 32 Comparator T2-LSBits T2-MSBits T1-LSBits T1-MSBits 25.23 Format 1−ae ae O1 { T1 O2 T2 { tWindow ≈ −1/[FS x ln(1−ae)] Where FS = Audio Sample Frequency CH1/CH2 = 0xB4 CH3 = 0xB9 CH1/CH2 = 0xB3 CH3 = 0xB8 25.
1−17 Slave Addr Ack Subaddr m Ack 0000 s b m 0000 s b m 0000 s b m 0000 s b m 0000 s b xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxx Ack xxx Ack xxx Ack xxx Ack xxx Ack Slave Addr Ack Subaddr m Ack 0000 s xxx Ack b m 0000 s xxx Ack b S VU Meter Output = 0xFE S Slave Addr Slave Addr Ack Ack Subaddr Subaddr Ack Ack Ack Ack Ack Ack Ack xxxxx.xxx xxxxx.xxx xxxxx.xxx xxxxx.xxx xxxxx.xxx xxxxx.xxx Ack Ack xxxxx.xxx xxxxx.xxx Ack xxxxx.xxx Ack Ack xxxxx.xxx xxxxx.
1−18 Σ Σ Σ Dither 1 Dither 2 Dither 3 Slave Addr Slave Addr Subaddr Ack Ack xxxxxxxx xxxxxxxx Ack Subaddr Ack St6 St5 St4 St3 St2 St 1 p 00000000 Sampler xxxxxxxx xxxxxxxx 0.5 Ack 0xC7 0.
1−19 LRCLK Subaddr 0xEF Microprocessor D D D Q Q Q Q 15 Sample Logic Decode 0 Down Counter S Slave Addr Ack READ Microprocessor EN Bus D 16 8 7 0 Subaddr LD Reset S Slave Addr Ack Reset 31 24 23 0xEE 16 15 Watchdog Counter Microprocessor Control 8 23 16 15 8 7 0 7 0 3 2 1 0 Ack 4 3 GPIO_in_out Microprocessor Clock 1 (Default State) Disables Watchdog Timer Ack 00000000 Ack 00000000 Ack 00000000 Ack 0000000x Ack Decode 216 Subaddr 0xEB 31 24 Determines How
1−20 S Slave Addr Ack 0xF2−0xF4—See Subaddress 0xA2 tTransition = TBLC[7:0] x 1/LRCLK 0xF1 Ack Bass Filter Set N Subaddr 24 00000000 31 Ack 16 8 xxxxxxxx 0 Ack CH1−CH3 Volume CMDS tTransition = TBLC[7:0] x 1/LRCLK Treble and Bass Slew Rate TBLC[7:0] v Ack 0000000 s Ack c 15 Treble Filter Set N 00000000 23 7 Master Mute/Unmute 0xF0—See Subaddress 0xA2 0xF1—Also See Subaddress 0xA2 and Subaddress 0xF5 Reserved/Factory Test Subaddresses GPIO Port I/O Values and GPIO Parameters 0xEC–0
Subaddress—Bass and Treble Shelf Filter Parameters Treble/Bass Slew Rate Selection S 0xF1 Slave Addr Ack Subaddr CH3 7 Ack CH2 00000000 Ack 00000000 V Ack 0000000 S Ack C S Slave Addr Ack Subaddr Ack 00000000 Ack 00000xxx Ack 00000xxx Ack 00000xxx xxxxxxxx Ack Treble/Bass Slew Rate = TBLC (Slew Rate = TBLC/Fs, Where Fs = Audio Sample Rate) CH1 Bass Filter Set Selection 0xF5 0 Ack CH2 CH3 CH1 Treble Filter Set Selection S 0xF7 Slave Addr Ack CH3 Subaddr Ack CH2 00000
÷32 ÷64 ÷128 ÷192 ÷256 ÷384 ÷512 Ack 0 1 x11 PLL SCLKOUT1 Ack 29 MUX 0 1 2 0 1 2 3 4 5 6 7 ÷2 ÷4 ÷8 ÷16 ÷32 XTALI SCLKIN MUX 0 1 0 1 2 3 4 5 6 7 MUX 22 IMS 23 32-bit 16-bit (default) 18-bit 20-bit 24-bit 32-bit 32-bit 32-bit Word Size 15 16 7 8 IM[3:0] DWFMT 15 8 0 0 Mode Ack OM[3:0] IOM Discrete, left-justified Discrete, left-justified (default) Discrete, right-justified Discrete, I2S Discrete, 16-bit packed TDM_LJ_8 TDM_LJ_6 TDM_LJ_4 TDM_I2S_8 TDM_I2S_6 TDM_I2S_4 TDM_20B
1−23 S Slave Addr Ack Subaddr Ack 00000000 Ack 0xFB ÷10 Ack I2C Master SCL 00000000 I2C Module I2C_SDA 00000000 1/(M+1) Ack n[2:0] 0 0xxxxxxx 3 2 1 0 ÷4 MUX MICROCLK_DIV m[3:0] 6 Microprocessor Clock I2C Sampling Clock ÷2N I2C_SCL I2C M AND N ASSIGNMENTS I2C M AND N ASSIGNMENTS Ack Digital Audio Processor Clock I2C Block
Delay/Reverb Assignments 0xFA Delay S Delay CH1 = 2 × {D1[11:0] + 1} Delay CH2 = 2 × {D2[11:0] + 1} Slave Addr Ack Subaddr Reverb m l m l Ack 0000 s xxx Ack xxxxxxx s Ack 0000 s xxx Ack xxxxxxx s Ack D1 and R1 b b b b l m l m 0000 s xxx Ack xxxxxxx s Ack 0000 s xxx Ack xxxxxxx s Ack D2 and R2 b b b b l m l m 0000 s xxx Ack xxxxxxx s Ack 0000 s xxx Ack xxxxxxx s Ack D3 and R3 b b b b Note: 2 × (D1 + D2 + D3) + 3 × (R1 +R2 +R3) ≤ 4076 Delay CH3 = 2 × {D3[11:0] + 1} Reserved Reverb CH1 = 2 × {R1[1
SUBADDRESS(ES) 0xFC—See Subaddress 0x00 PARAMETER(S) Ending I2C Check Word 0xFD−0xFE—See Subaddress 0xBB Spectrum Analyzer/VU Meter Outputs 0xFF—Volume Busy Flag Volume Flag S Slave Addr Ack Subaddr Ack 0000000x S S Volume Flag = 0 ⇒ No volume commands are active. Volume Flag = 1 ⇒ One or more volume commands are active.
1−26
2 Hardware Architecture Figure 2−1 depicts the hardware architecture of the chip.
SCLKIN MCLKI XTALI XTALO MCLKO ÷2 PLL1 PLL0 SCLKOUT1 ÷2 M U X MCLK ÷Z M U X ÷2 M U X PLL (x11) ÷4 M U X M U X ÷X M U X ÷Y SDIN1 MICROCLK_DIV SCLKOUT2 M U X OSC ÷2 LRCLK ORIN PLL and Clock Management 32 Bits 32 Bits 4K × 16 Delay Line RAM 32 Bits Dual Port Data RAM SDOUT1 Coefficient RAM Program ROM 256 Bits 32 Bits Arithmetic Engine SDIN2 DAP Instruction Decoder/Sequencer SDOUT2 76-Bit Adder 32 Bits SDIN3 Regs Regs Digital Audio Processor (DAP) Arithmetic Unit 64 B
2.1 Input and Output Serial Audio Ports (SAPs) The TAS3103A accepts data in various serial data formats including left-/right-justified and I2S, 16 through 32 bits, discrete, or time-division multiplex (TDM). Sample rates from 8 kHz through 96 kHz are supported. Each TAS3103A has four input serial ports and three output serial ports, labeled SDIN[4:1] and SDOUT[3:1], respectively. All ports accommodate stereo data formats, and SDIN1 and SDOUT1 also accommodate TDM data formats.
A 16-bit field contained in the 32-bit word located at I2C subaddress 0xF9 configures both the input and output serial audio ports. Figure 2−4 illustrates the format of this 16-bit field. The data is shown in the transmitted I2C protocol format, and thus, in addition to the data, the start bit S, the slave address, the subaddress, and the acknowledges required by every byte are also shown.
Enter Yes Vol Busy No Issue Mute Command Yes Vol Busy No Issue SAP Configuration Change Command Issue Unmute Command Yes Vol Busy No Mute Command = 0x00000007 at subaddress 0xF0 Unmute command = 0x00000000 at subaddress 0xF0 SAP configuration subaddress = 0xF9 Volume busy flag = LSB of subaddress 0xFF. Logic 1 = busy Exit Figure 2−5.
In Figure 2−10 and Figure 2−11, the paired TDM output formats 0101 and 1000 are unique in that each format, in effect, services two distinct industry formats. For these two modes, if register Y in chip AB = 1 is set to zero (by appropriate output mixer coefficient settings), the resulting format is a standard 8-CH TDM format. This option is illustrated in Figure 2−7.
2−7 All options valid All options valid except 32-bit 8-CH transfer, leftjustified 8-CH transfer, I2S(5) 0101 1000 All options valid All options valid except 32-bit IW[2:0] = 011 All options valid All options valid except 32-bit 4-CH, I2S(5) 6-CH, 20-bit 6-CH data, 8 CH transfer, left-justified 6-CH data, 8 CH transfer, I2S(5) 1010 1011/1111(4) 1100 1110 All options valid except 32-bit 4-CH, left-justified 6-CH, I2S(5) 0111 1001(3) All options valid IW[2:0] = 001 16-bit packed 0100 6
2−8 All options valid All options valid All options valid except 32-bit 6-CH, 2-chip, leftjustified 6-CH, 2-chip, I2S(2) 4-CH, left-justified 4-CH, I2S(2) 0110(1) 1001(1) 0111 1010 6-CH, 20-bit 1111 1110 OW[2:0] = 011 All options valid 6-CH data, All options valid except 32-bit 8-CH transfer, I2S(2) 1100 1101(1) All options valid 6-CH data, 8-CH transfer, left-justified 6-CH, left-justified OW[2:0] = 011 6-CH, 2-chip, 20-bit 1011 All options valid except 32-bit 8-CH, 2-chip, I2S(2)
2−9 OW[2:0] = 001 0011 16-bit packed All options valid except 32-bit I2S(2) 0100 All options valid Right-justified 0010 All options valid WORD SIZE Left-justified FORMAT 000X(1) OM[3:0] V 16 16 R L U 32 V R 32 U L SDOUT1 SCLKs SCLKs 0 0 1 1 1 1 18 Bit 20 Bit 24 Bit 32 Bit (32) (32) 0 0 (32) 16 Bit 1 1 0 0 1 1 0 0 IW1 1 0 1 0 1 0 1 0 IW0 INPUT IW[2:0] IW2 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 OW1 1 0 1 0 1 0 1 0 OW0 OUTPUT OW[2:0] OW2
TAS3103A SDOUT1 U1 (AB = 1) LRCLK L LRCLK R L R ORIN U2 U 32 V 32 32 W 32 32 X SDOUT1U1 32 32 32 W 0 X 32 32 32 SCLKs UU2 UU1 VU2 VU1 WU2 WU1 XU2 XU1 32 32 32 32 32 32 32 32 SCLKs 32 SCLKs TAS3103A SDOUT1 U1 U 32 V 32 32 32 32 SCLKs U2 (AB = 0) ORIN Figure 2−10.
2−11 SDIN4 SDIN3 SDIN2 SDIN1 SDIN4 SDIN3 SDIN2 SDIN1 G E C A Serial Input Rx Holding Regs Regs H F D B Input Holding Regs H F D B Input Holding Regs Sample Time N G E C A Serial Input Rx Holding Regs Regs Sample Time N SDIN1 Sample Time N G E C H F D CH3 CH2 CH3 CH2 CH1 Z Y X W V SDIN4 SDIN3 SDIN2 G E C H F D B Input Holding Regs Figure 2−12.
LRCLK SDIN L2 R3 L4 L2, R2 R4 L3, R3 Load Output Holding Registers Holding Register ⇒ Output Serial Registers L0 SDOUT Processing Cycle 1.5Cycle Delay L3 L1, R1 Processing Cycle 2.5Cycle Delay R2 L1, R1 R0 L1 R1 L2 L3, R3 L2, R2 Load Output Holding Registers Holding Register ⇒ Output Serial Registers SDOUT R0 L1 R1 L2 R2 L3 (a) Left-Justified Input / I2S Output LRCLK SDIN Processing Cycle 2.
Table 2−1 lists all viable clock selections for a given audio sample rate (LRCLK). The table only includes those clock choices that allow enough processing throughput to accomplish all tasks within a given sample time (Ts = 1/LRCLK). For each entry in the table, the DAP processing time is given in terms of whether the time is greater than 0.5 Ts (resulting in an input-to-output delay of 2.5 Ts), or less than 0.5 Ts (resulting in an input-to-output delay of 1.5 Ts).
2.2 DPLL and Clock Management Clock management for the TAS3103A consists of two control structures: • Master clock management: oversees the selection of the clock frequencies for the microprocessor, the I2C controller, and the digital audio processor (DAP). The master clock (MCLKI or XTALI) serves as the source for these clocks. In most applications, the master clock is input to an on-chip digital phase-locked loop (DPLL), and the DPLL output is used to drive the microprocessor and DAP clocks.
Table 2−2. Sample Rate and CLK Ratios Sample Rate DAP Cycles Req’d MCLK RATIO 768 512 384 256 192 128 PLL[1:0] = 00 96 134,400 135.168 88.1 123,340 124.0448 48 67,200 44.1 61,740 32 44,800 135.168 135.168 101.376 67.584 124.1856 93.1392 62.0928 90.112 67.584 45.056 24 33,600 135.168 101.376 67.584 50.688 33.792 22.1 30,940 124.4672 93.3504 62.2336 46.6752 31.1168 8 11,200 45.056 33.792 22.528 16.896 96 134,400 135.168 88.1 123,340 124.0448 67.
Enable Mute These two steps ensure that the device does not produce audible artifacts during the sample rate changes Yes Vol Busy No Set RST Low Change Sample Rate No Are Clocks Stable? Yes Set RST High Wait 5 ms Set Clock and SAP Parameters Wait 1 ms Restore Volume Settings Figure 2−14.
2.2.2 The Microprocessor Clock and I2C The selected microprocessor clock is also used to drive the clocks used by the I2C control block. Two parameters, N and M, define the clocks used by the I2C control block. The I2C control block sampling frequency is set by 1/2N, where N can range in value from 0 to 7. A 1/(1 + M) divisor followed by a 1/10 divisor generates the data bit clock (SCL). This derived SCL clock is only used when the I2C control block is set to master mode (input pin I2CM_S = 1).
When the SAP is in the master mode, it uses the MCLKI/XTALI master clock to drive the serial port clocks SCLKOUT1, SLCKOUT2, and LRCLK. When the SAP is in the slave mode, LRCLK is an input and SCLKOUT2 and SCLKOUT1 are derived from SCLKIN. As shown in Figure 2−15, SCLKOUT1 clocks data into the input SAP and SCLKOUT2 clocks data from the output SAP. Two distinct clocks are required to support TDM-to-discrete and discrete-to-TDM data format conversions.
I2C Bus Controller 2.3.2 The TAS3103A has a bidirectional, two-wire, I2C-compatible interface. Both 100-kbps and 400-kbps data transfer rates are supported, and the TAS3103A controller can serve as either a master I2C device or a slave I2C device. Master/slave operation is defined by the logic level input into pin I2CM_S (logic 1 = master mode, logic 0 = slave mode). If the voltage input level to I2CM_S is changed, the TAS3103A must be reset.
be included in the data written. There cannot be a separate write transaction to supply the subaddress, as was required for read transactions. If a subaddress assignment only write transaction is followed by a second write transaction supplying the data, erroneous behavior results. The first byte in the second write transaction is interpreted by the TAS3103A as another subaddress replacing the one previously written.
Table 2−4.
2.3.2.2 I2C Slave Mode Operation The I2C slave mode permits configuration parameters (other than volume via the GPIO pins for the I2C master mode) to be changed. The TAS3103A can detect and reset the I2C interface when an invalid I2C command is received. This feature is enabled by setting the I2C configuration control value N to zero. This feature is also enabled by the default setting, 0x0000 0040, of the I2C configuration control register 0xFB.
simply does not receive all the data. If the master device issues more data-received acknowledges than required to receive the data for a given subaddress, the master device simply receives complete or partial sets of data, depending on how many data-received acknowledges are issued from the subaddress(es) that follow. I2C read transactions, both sequential and random, can impose wait states.
47 S S S S 40 S 39 S 32 31 Overhead/Guard Bits 16-Bit Audio 18-Bit Audio 24 23 22 21 20 19 20-Bit Audio 24-Bit Audio 32-Bit Audio 16 15 8 7 Precision/Noise Bits 0 Figure 2−19. DAP Arithmetic Unit Data Word Structure The arithmetic engine is a 48-bit (25.23-format) processor consisting of a general-purpose 76-bit arithmetic logic unit (ALU) and function-specific arithmetic blocks.
8-Bit ALU Operation (Without Saturation) Rollover 10110111 (−73) −73 + 11001101 (−51) + −51 10000100 (−124) −124 + 11010011 (−45) + −45 01010111 (57) + 00111011 (59) 10010010 (−110) −169 + 59 −110 Figure 2−20. DAP ALU Operation With Intermediate Overflow The DAP processing clock is set by pins PLL0 and PLL1, with the source clock XTALI or MCLKI. The DAP operates at speeds up to 136 MHz, which is sufficient to process 96-kHz audio. 2.
3.3 V TAS3103A SN74LVC1G07 10 kΩ 26 RST RST 2 µF Figure 2−22. External Power-Good Reset-Control Circuit Note that RST implements an asynchronous clear. This control can respond to narrow negative signal transitions. Some applications, therefore, might require a high-frequency capacitor on the RST pin to remove unwanted noise excursions. 2.
The watchdog timer is governed by the parameter GPIOFSCOUNT in subaddress 0xEF and the LSB of the 32-bit word at subaddress 0xEB. The default value of the LSB of the 32-bit word at subaddress 0xEB is 1, and this value disables the watchdog timer. The GPIOFSCOUNT is also used in other functions and balancing the needs of these other functions regarding GPIOFSCOUNT with the requirements of the watchdog timer is an involved process.
Table 2−6. GPIO Port Functionality—I2C Master Mode GPIO PORT FUNCTION GPIO0 (pin 18) Volume up—CH1 and CH2 GPIO1 (pin 19) Volume down—CH1 and CH2 GPIO2 (pin 20) Volume up—CH3 GPIO3 (pin 21) Volume down—CH3 GPIOFSCOUNT also governs the rate at which the power-down pin PWRDN is sampled and the rate at which the watchdog counter is reset. GPIOFSCOUNT then cannot be independently used to tune the volume adjustment.
2−29 GPIO Reads GPIO Data Samples LRCLK GPIO Pin Input Read = 1 Read = 1 Adjust 0.5 dB Adjust 5 dB Read = 0 GPIO_samp_int = 2 Read = 0 Adjust 5 dB Read = 0 Read = 1 Read = 1 Figure 2−24. Volume Adjustment Timing—Master I2C Mode Adjust 0.5 dB Read = 0 GPIOFSCOUNT = 3 Adjust 0.5 dB Read = 0 Adjust 0.
2−30
3 Firmware Architecture 3.1 I2C Coefficient Number Formats The firmware for the TAS3103A is housed in ROM resources within the TAS3103A and cannot be altered. However, mixer gain, level offset, and filter tap coefficients, which can be entered via the I2C bus interface, provide a user with the flexibility to set the TAS3103A to a configuration that achieves the system-level goals. The firmware is executed in a 48-bit signed fixed-point arithmetic machine.
Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit number (4-byte or 8-digit hexadecimal number) is shown in Figure 3−3. Fraction Digit 6 Sign Bit Integer Digit 1 u u u u Coefficient Digit 8 S x x x Coefficient Digit 7 Fraction Digit 1 x.
Figure 3−5 shows the derivation of the decimal value of a 48-bit 25.23-format number. 223 Bit 222 Bit 20 Bit 2−1 Bit 2−23 Bit (1 or 0) y 223 + (1 or 0) y 222 + … + (1 or 0) y 20 + (1 or 0) y 2−1 + … + (1 or 0) y 2−23 Figure 3−5. Alignment of 25.23 Coefficient in 32-Bit I2C Word Two 32-bit words must be sent over the I2C bus to download a level or threshold coefficient into the TAS3103A. The alignment of the 48-bit, 25.
3.2 Input Crossbar Mixers The TAS3103A has four serial input ports—SDIN1, SDIN2, SDIN3, and SDIN4. SDIN1, SDIN2, and SDIN3 provide the input resources to process 5.1-channel audio in two TAS3103A chips. SDIN4 provides the capability to multiplex between a full 5.1-channel system and a stereo source or an information/warning audio message as might be found in an automotive application. Each serial input port is assigned two internal processing nodes.
SDIN1 LRCLK L Internal Processing Nodes Internal Processing Nodes R A A L B B R time SDIN2 LRCLK L Internal Processing Nodes R time R C C L D D Internal Processing Nodes Internal Processing Nodes R E E L F F Internal Processing Nodes Internal Processing Nodes R G G L H H SDIN3 LRCLK L R time SDIN4 LRCLK L time Internal Processing Nodes SDIN1 R (a) Discrete Mode − For I2S Format, Polarity of LRCLK Opposite That Shown (b) TDM Mode Figure 3−7.
3−6 Input Crossbar Mixers f b h c g a 4 Biquad Filters 4 Biquad Filters 4 Biquad Filters 4 Biquad Filters 4 Biquad Filters 4 Biquad Filters Reverb Delay Reverb Delay Reverb Delay 3D Effects Block e d aa Figure 3−8.
3−7 f h Monaural CH3† Monaural CH2† Monaural CH1† Figure 3−9. Input Mixer Topology—Internal Processing Nodes G and H † Monaural channels consist of 12 biquad filters, followed by bass and treble processing, followed by volume and loudness processing, followed by dynamic range control, followed by dither processing. See the TAS3103A Firmware Block Diagram in Appendix A.
3.3 3D Effects Block The 3D effects block, shown in Figure 3−10, performs the first suite of processing tasks conducted on the incoming serial audio data streams. The TAS3103A has three monaural channels—CH1, CH2, and CH3. CH1 and CH2 share the same effects block, as well as the same dynamic range compression block. CH3 has its own effects block and its own dynamic range compression block. In typical two-TAS3103A-chip configurations for processing 5.
3−9 Mixer Gain Coefficient Subaddress Format Node H Processing Node G Processing A, B, C, D, E, F Processing Nodes Reverb Mixers f 0x33 b 0x28 h 0x26 c 0x25 g 0x27 a 4 Biquad Filters 0x48 − 0x4B 4 Biquad Filters 0x38 − 0x3B 4 Biquad Filters 0x40 − 0x43 4 Biquad Filters 0x44 − 0x47 4 Biquad Filters 0x3C − 0x3F 4 Biquad Filters 0x34 − 0x37 0x30 0x2F 0x32 0x31 0x2E 0x2D g1 Reverb Delay 0xFA Delay Line g0 g0/g1 = 0x4E 0xFA Delay Line g0 g1 Reverb Delay g1 Rever
3.4 Biquad Filters The TAS3103A has 73 biquad filters . The breakout of the biquad filters per functional element is given in Table 3−1. Table 3−1.
The direct-form I structure provides a separate delay element and mixer (gain coefficient) for each node in the biquad filter. Each mixer output is a signed 76-bit product of a signed 48-bit data sample (25.23-format number) and a signed 28-bit coefficient (5.23-format number). A 76-bit ALU in the TAS3103A allows the 76-bit resolution to be retained when summing the mixer outputs (filter products).
Reverb Block Gains S S Slave Addr Slave Addr Ack Ack Subaddr Subaddr m Ack 0000 s xxx b m 0000 s xxx b m Ack 0000 s xxx b m 0000 s xxx b Reverb Block Subaddress CH1 0x4C CH2 0x4D CH3 0x4E Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxxxx l Ack xxxxxx s b l Ack xxxxxx s b l Ack xxxxxx s b l Ack xxxxxx s b Ack G0 Ack G1 Ack G0 Ack G1 Gain Coefficient G0 (Format = 5.
Treble/Bass Slew Rate Selection S 0xF1 Slave Addr Ack 7 Subaddr Ack CH2 CH3 00000000 Ack V Ack 0000000 C Ack S 00000000 S Slave Addr Ack Subaddr Ack 00000000 Ack 00000xxx Ack 00000xxx Ack Ack Treble/Bass Slew Rate = TBLC (Slew Rate = TBLC/Fs, Where Fs = Audio Sample Rate) CH1 Bass Filter Set Selection 0xF5 0 xxxxxxxx 00000xxx Ack CH2 CH3 CH1 Treble Filter Set Selection S 0xF7 Slave Addr Ack CH3 Subaddr Ack CH2 00000000 Ack 00000xxx Ack 00000xxx Ack 00000xxx
CAUTION: No soft transition is implemented when changing bass and treble filter sets; soft transitions only apply when adjusting gains (shelves) within a given filter set. The variable TBLC should be set so that the dwell time at each shelf is never less than 32 audio sample periods; otherwise, audio artifacts could be introduced into the audio data stream.
CH3 CH2 CH1 Bass Filter Set Selection 0xF5 S Slave Addr Ack Subaddr Ack 00000000 Ack 00000101 Ack CH3 00000101 Ack CH2 00000101 Ack Filter Set 5 Selected Ack Filter Set 3 Selected Ack Filter Shelf 0x55 Selected CH1 Treble Filter Set Selection 0xF7 S Slave Addr Ack Subaddr Ack 00000000 Ack 00000011 Ack CH3 00000011 Ack CH2 00000011 CH1 Bass Shelf Selection (Filter Index) 0xF6 S Slave Addr Ack Subaddr Ack 00000000 Ack 01010101 Ack CH3 01010101 Ack CH2 010
Table 3−3. Treble Shelf Filter Indices for 1/2-dB Adjustments ADJUSTMENT (dB) INDEX(1) ADJUSTMENT (dB) INDEX(1) ADJUSTMENT (dB) INDEX(1) 18 0x01 5.5 0x63 −7 0x80 17.5 0x09 5 0x65 −7.5 0x81 17 0x10 4.5 0x66 −8 0x82 16.5 0x16 40 0x68 −8.5 0x83 16 0x1C 3.5 0x69 −9 0x84 15.5 0x22 3 0x6B −9.5 0x85 15 0x28 2.5 0x6C −10 0x86 14.5 0x2D 2 0x6D −10.5 0x87 0x88 14 0x31 1.5 0x6F −11 13.5 0x35 1 0x70 −11.5 0x89 13 0x3A 0.5 0x71 −12 0x8A 12.
Start Write 0x00, 0x06, 0x00, 0xCD subaddress 0xEC Read 8-byte output from subaddress 0xED No 8th Byte = 0 CH1 Treble Yes Write 0x00, 0x06, 0x00, 0xD1 subaddress 0xEC Read 8-byte output from subaddress 0xED No 8th Byte = 0 CH1 Bass Yes Write 0x00, 0x06, 0x00, 0xCE subaddress 0xEC Read 8-byte output from subaddress 0xED No 8th Byte = 0 CH2 Treble Yes Write 0x00, 0x06, 0x00, 0xD2 subaddress 0xEC Read 8-byte output from subaddress 0xED No 8th Byte = 0 CH2 Bass Yes Write 0x00, 0x06, 0x00, 0x
3.6 Soft Volume/Loudness Processing Each of the three monaural channels in the TAS3103A has dedicated soft volume control and loudness compensation. Volume level changes are issued by I2C bus commands in the I2C slave mode and by setting the appropriate GPIO pin to logic 0 in the I2C master mode. Commanded changes in volume are implemented softly, using a smooth S-curve trajectory to transition the volume to the newly commanded level. Volume commands are formatted as signed 5.23 numbers.
TAS3103A, volume commands received for the other two monaural channels are not acted on until the active volume transition completes. When the active volume transition does complete, the latest volume command received for the three monaural channels during the previous soft volume transition time are serviced. LRCLK should not be stopped during a volume transition.
The volume control range is 0 = −∞ to 2−23 = −138.47 dB to 24 − 2−23 = 24.08 dB. Volume control is achieved by means of a 5.23-format gain coefficient that is applied to a linear mixer. The volume gain setting realized, for a given volume gain coefficient is: Gain = 20 log (Volume_Gain_Coefficient) Several techniques of volume management for a linear volume control process are: • Precise calculations involving logarithms can be employed. • A high-resolution gain table, with entries for every 0.
Table 3−4. Volume Adjustment Gain Coefficients GAIN (dB) GAIN (FLOAT) GAIN (COEFFICIENT) GAIN (dB) GAIN (FLOAT) GAIN (COEFFICIENT) 24 15.84893192 07EC A9CD 2 1.25892541 00A1 2477 23.5 14.96235656 077B 2E7F 1.5 1.18850223 0098 20D7 23 14.12537545 0710 0C4D 1 1.12201845 008F 9E4C 22.5 13.33521432 06AA E84D 0.5 1.05925373 0087 95A0 22 12.58925412 064B 6CAD 0 1 0080 0000 21.5 11.88502227 05F1 4868 −0.5 0.94406088 0078 D6FC 21 11.22018454 059C 2F01 −1 0.
Table 3−4. Volume Adjust Gain Coefficient (Continued) 3−22 GAIN (dB) GAIN (FLOAT) GAIN (COEFFICIENT) GAIN (dB) GAIN (FLOAT) GAIN (COEFFICIENT) −20 0.1 000C CCCC −42 0.00794328 0001 0449 −20.5 0.09440609 000C 157F −42.5 0.00749894 0000 F5B9 −21 0.08912509 000B 6873 −43 0.00707946 0000 E7FA −21.5 0.08413951 000A C515 −43.5 0.00668344 0000 DB00 −22 0.07943282 000A 2ADA −44 0.00630957 0000 CEC0 −22.5 0.07498942 0009 9940 −44.5 0.00595662 0000 C32F −23 0.
Table 3−4. Volume Adjust Gain Coefficient (Continued) GAIN (dB) GAIN (FLOAT) GAIN (COEFFICIENT) GAIN (dB) GAIN (FLOAT) GAIN (COEFFICIENT) −64 0.00063096 0000 14AC −86 5.01188E−05 0000 01A4 −64.5 0.00059566 0000 1384 −86.5 4.73152E−05 0000 018C −65 0.00056234 0000 126D −87 4.46684E−05 0000 0176 −65.5 0.00053088 0000 1165 −87.5 4.21696E−05 0000 0161 −66 0.00050119 0000 106C −88 3.98108E−05 0000 014D −66.5 0.00047315 0000 0F81 −88.5 3.
Table 3−4. Volume Adjust Gain Coefficient (Continued) GAIN (dB) GAIN (FLOAT) GAIN (COEFFICIENT) GAIN (dB) GAIN (FLOAT) GAIN (COEFFICIENT) −108 3.98108E−06 0000 0021 −122.5 7.49894E−07 0000 0006 −108.5 3.75838E−06 0000 001F −123 7.07946E−07 0000 0005 −109 3.54814E−06 0000 001D −123.5 6.68344E−07 0000 0005 −109.5 3.34966E−06 0000 001C −124 6.30958E−07 0000 0005 −110 3.16228E−06 0000 001A −124.5 5.95662E−07 0000 0004 −110.5 2.98538E−06 0000 0019 −125 5.
data that falls in the subaddress range 0x01 through 0xD1 after issuing an I2C command to change the volume level on one of the three monaural channels, the busy bit at subaddress 0xFF must be monitored to determine when the volume activity has ceased and it is safe to resume I2C read activity at subaddresses 0x01 through 0xD1. A value of 0 in the least-significant bit of the byte output on reading subaddress 0xFF signifies that all volume transition activity has completed. 3.6.
3−26 Volume Commands I2C Bus Slave Addr Ack Subaddr Ack S S xxxxxxxx Ack xxxxxxxx CCC Ack xxxxxxxx Ack xxxxx HHH Ack 321 Ack m Subaddr Ack 0000 s xxx Ack xxxxxxxx b Ack xxxxxxxx l Ack xxxxxxx s Ack b Volume Command ttransition Commanded Volume 48 28 VSC S Ack xxxxxxxx m 0000 s xxx Ack xxxxxxxx b a2 28 28 a1 Ack xxxxxxxx Ack xxxxxxxx m 0000 s xxx Ack xxxxxxxx b m 0000 s xxx Ack xxxxxxxx b Ack xxxxxxxx Ack xxxxxxxx ( ) LG m 0000 s xxx Ack xxxxxxxx b Σ 48 Σ 48 48 Ack l xxxxxx
If G is set to 0 and O is set to 0, loudness compensation is disabled. If G is set to 0 and O is set to 1, the biquad-filtered audio is directly added to the volume-level-adjusted audio. Typically, LG and LO are used to derive the desired loudness compensation function, G is used to turn loudness compensation on and off, and O is used to enable and disable the biquad filter output when automatic volume tracking is turned off. 3.6.
Start 0 Delay Memory Allocation − CH1 (CH1 Delay Assignment = PCH1) Delay CH1 Stop Start 2(PCH1 + 1) − 1 2(PCH1 + 1) Delay CH2 Delay Memory Allocation − CH2 (CH2 Delay Assignment = PCH2) Stop Start Delay Memory Allocation − CH3 (CH3 Delay Assignment = PCH3 = 0) Stop Start Delay Memory Allocation − Reserved (Reserved Delay Assignment = 0) Stop Start 2(PCH1 + PCH2 + 2) − 1 2(PCH1 + PCH2 + 2) 2(PCH1 + PCH2 + 2) + 1 2(PCH1 + PCH2 + 3) 2(PCH1 + PCH2 + 3) + 1 2(PCH1 + PCH2 + 4) ÎÎ ÎÎ ÎÎ Delay CH3 (P
CASE 1: Maximum Length − One Reverb Delay Line P Reverb_max_CH2 + [(4096 * 5 * 2 * 2 * 2 * 3 * 3) B 3] * 1 + 1358 2 ³ 1358 3 CH1 CH2 CH3 CH1 CH3 Delay Reverb Reserved L length requires L + 1 delay elements CASE 2: Maximum Length − One Delay Line P Delay_max_CH3 + [(4096 * 5 * 2 * 2 * 3 * 3 * 3) B 2] * 1 + 2038 CH1 CH2 CH1 CH2 CH3 Delay Reverb Reserved L length requires L + 1 delay elements CASE 3: Maximum Length − Three Equal-Length Reverb Delay Lines P Reverb_max_CH1, CH2, CH3 + |{[(4096 * 5 * 2 *
Commands to reconfigure the reverb delay and delay lines should not be issued as stand-alone commands. When new delay assignments are issued, the content of the 4K memory resource used to implement the delay lines is not flushed. It takes a finite time for the memory to refill with samples in correspondence with its new assignments, and until this time has elapsed, audio samples can be output on the wrong channel.
Figure 3−22 illustrates a typical DRC transfer function. DRC − Compensated Output Region 0 Region 1 Region 2 k2 k1 1:1 Transfer Function Implemented Transfer Fucntion k0 O2 O1 T1 T2 DRC Input Level Figure 3−22. DRC Transfer Function Structure The three regions shown in Figure 3−22 are defined by three sets of programmable coefficients: • Thresholds T1 and T2—define region boundaries. • Offsets O1 and O2—define the DRC gain coefficient settings at thresholds T1 and T2, respectively.
• 3.7.1 Slopes k0, k1, and k2 define whether compression or expansion is to be performed within a given region, and the degree of compression or expansion to be applied. Slopes are programmed as 28-bit (5.23-format) numbers. DRC Implementation Figure 3−23 shows the three elements comprising the DRC: (1) an rms estimator, (2) a compression/expansion coefficient computation engine, and (3) an attack/decay controller.
3−33 Audio Input CH2 Audio Input CH1 or CH3 5.23 Format RMS Voltage Estimator 32 Comparator T2-MSBits T2-LSBits Ack Ack 1−ae O1 { T1 O2 T2 { CH1/CH2 = 0xB3 CH3 = 0xB8 25.23 Format K2 K1 K0 CH1/CH2 = 0xB5 CH3 = 0xBA td ta ≈ −1/[FS x ln(1−aa)] td ≈ −1/[FS x ln(1−ad)] Cut Attack / Decay Control ta l Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxxxs b l Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxxxs b l Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxxxs b l Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxxxs b Volume 5.
3.7.2 Compression/Expansion Coefficient Computation Engine Parameters Seven programmable parameters are assigned to each DRC block: two threshold parameters, T1 and T2; two offset parameters, O1 and O2; and three slope parameters, k0, k1, and k2.
O INPUT + O ) 24.0824 dB DESIRED 6.0206 Gains or boosts are represented as negative numbers; cuts or attenuation are represented as positive numbers. For example, to achieve a boost of 21 dB at threshold T1, the I2C coefficient value entered for O1 must be: O1 INPUT + –21 dB ) 24.0824 dB + 0.51197555 6.0206 + 0.1000_0011_0001_1101_0100 + 0x00000041886A in 25.23 format More examples of offset computations follow. 3.7.2.
3.7.3 DRC Compression/Expansion Implementation Examples The following four examples illustrate the steps that must be taken to calculate the DRC compression/expansion coefficients for a specified DRC transfer function. The first example is an expansion/compression/expansion implementation without discontinuities in the transfer function and represents a typical application. This first example also illustrates one of the three modes of DRC saturation—32-bit dynamic range limitation saturation.
0-dB Gain CH1 Processing 48-Bit DAP Word ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 48-Bit DAP Word 24 47 Headroom 40 39 Headroom 1 2 8 2 0 4 B B 3 i 2 B i t i t B t i t SAP Input Port ÎÎÎÎÎ ÎÎÎÎÎ 47 44 43 1 2 8 2 0 4 B B 3 i 2 B i t i t B t i t 1 6 B i t 1 6 B i t DRC 16 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Resolution Resolution 8 7 0 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 8 7 24 0 CH2 Processing 0-dB Gain Figure 3−24.
O1 INPUT + 1 [*7.5 ) 24.0824] + 2.754277 6.0206 + 0 0010.1100 0001 0001 1000 0100 110 + 0x0000 0160 8C26 in 25.23 format For input levels above the T2 threshold, the transfer function exhibits a 1:1.1 expansion. For input levels below T2, the transfer function exhibits a 2:1 compression. Also, by definition, it is seen that there is no discontinuity in the transfer function at T2. When the 2:1 compression curve in region 1 intersects the T1 threshold level, the output level is 7.
+30 +20 +10 0 −10 −20 −30 −40 1:1 Transfer Function −50 Implemented Transfer Function −60 Slope change points DRC − Compensated Output (dB) O2 = 30 dB −70 k2 = 1 : 1.1 −80 −90 −100 O1 = −7.5 dB −110 k1 = 2 : 1 −120 −130 −140 −150 −160 k0 = 1 : 1.05 −170 −180 −190 −200 −210 k = 1:1 (32-Bit Dynamic Range Saturation) −220 −220 −210 −200 −190 −180 −170 −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 T1 −60 −50 −40 −30 −20 −10 0 T2 DRC INPUT (dB) Figure 3−25.
The transfer curve remains a constant 24 dB above the 1:1 transfer curve for input levels above and below T2 until the computed DRC gain coefficient falls within the dynamic range of a 5.23-format number. For input levels above T2, k2 implements a 5:1 compression. At an input level 7.5 dB above T2 (−62.5 dB), the DRC transfer curve has risen 7.5/5 = 1.5 dB. The boost at this point is 30 dB – (7.5 dB – 1.5 dB) = 24 dB. The DRC has come out of gain saturation. For input levels above −62.
k = 1:1 (Gain Saturation) k2 = 5:1 − 40 −24 dB − 50 O2 = − 30 dB − 60 −24 dB −70 1:1 Transfer Function − 80 Ideal Transfer Function (Unlimited Resolution) − 90 − 100 Implemented Transfer Function k1 = 1 : 2 Slope change points − 110 DRC − Compensated Output (dB) − 120 − 130 − 140 − 150 − 160 − 170 O1 = 50 dB − 180 − 190 − 200 − 210 − 220 k0 = 2 : 1 − 230 − 240 − 250 − 260 − 192 dB − 270 − 280 − 62.
When T1 and T2 are set equal, the following questions arise: • If O1 ≠ O2, what roles do O1 and O2 have? • Which slope parameter, k0 or k1, has control of the transfer function for input levels below the common threshold point? • Does k2 control the transfer function for inputs above the common threshold point? This example addresses and answers those questions. Table 3−6.
0 −10 −20 −30 −40 DRC − Compensated Output (dB) 1:1 Transfer Function −50 Implemented Transfer Function −60 Slope change points −70 −80 −90 −100 −110 −120 k = 1:1 (Minimum Gain Saturation) −130 −140 −150 O2 = −20 dB k2 = ∞:1 −160 30 dB −170 −180 −190 −200 k = 1:1 (32-Bit Dynamic Range Saturation) O1 = 10 dB k0 = 2:1 −210 −14.7 dB −192 dB −220 −220 −210 −200 −190 −180 −170 −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 T1/T2 DRC INPUT (dB) Figure 3−27.
The horizontal slope of the transfer curve above the common threshold point does not remain horizontal indefinitely. At a point 158 dB above the common threshold point (−14.7-dB DRC input level), the transfer function has gone from a boost of 20 dB to a cut of 138 dB. A cut of 138 dB is the maximum cut possible for a 5.23-format gain coefficient (2−23 ≥ 23 octaves × 6 dB/octave = 138 dB). Thus, at a DRC input level of −14.7 dB, minimum gain saturation has been reached.
+30 +20 +10 0 −10 −20 −30 −40 DRC − Compensated Output (dB) 1:1 Transfer Function −50 Implemented Transfer Function −60 Slope change points −70 −80 −90 k = 1:1 Gain Saturation) −100 −110 O2 = 100 dB −120 k1 = 1:−1 −130 O1 = 0 dB k2 = 1:1.4 −140 −150 −160 −170 −180 k = 1:1 (32-Bit Dynamic Range Saturation) −190 −200 k0 = 1:1.
Table 3−7. DRC Example 4 Parameters DRC PARAMETER REQUIRED (SPECIFIED) VALUE (NET GAINSAP Input-DRC = 0 dB) T2 −22 dBInput ≥ −70 dBDRC T1 −102 dBInput ≥ −150 dBDRC O2 100 dB O1 0 dB k2 1:1.4 expansion k1 1:−1 transfer k0 1:1.5 expansion I2C COEFFICIENT VALUE −70/−6.0206 = 11.626748 = 0x0000 05D0 394825.23 format −150/−6.0206 = 24.91446 = 0x0000 0C75 0D0925.23 format (100 + 24.0824)/6.0206= 20.609640 = 0x0000 0A4E 08B025.23 format (0 + 24.0824)/6.0206 = 4.000000 = 0x0000 0200 000025.
3−47 CH3 CH2 CH1 GMix: q to r GMix: p to r GMix: o to r Node r Node q Node p GMix: p to t RMS Voltage Estimator Biquad 2 Ack b2 Ack b1 Ack b0 Ack a2 Ack a1 VU Meter Output 1 (Biquad 5) VU Meter Output 1 (Biquad 6) asa and (1−asa) Set Time Window Over Which RMS Value Is Computed tWindow ≈ −1/[Fs x ln(1−asa)] Where Fs = Audio Sample Frequency Figure 3−29.
Spectrum Analyzer and VU Meter Output 48-Bit RMS Estimate 31 0 48 0 1 1 0 0 1 0 11111.100 28 0 48 0 0 0 0 1 1 0 1 0 1 11100.101 1 48 0 0 0 18 0 1 0 1 0 1 1 0 0 00001.010 0 48 0 0 0 18 0 0 1 1 1 0 1 0 0 48 0 0 0 18 0 0 0 1 1 0 1 0 1 0 00000.110 00000.000 Figure 3−30. Logarithmic Number Conversions—Spectrum Analyzer/VU Meter The time window over which the rms estimate is conducted is programmable via the I2C bus (subaddress 0xBB).
3.9.1 Dither Seeds The dither circuit consists of two linear feedback shift registers—LFSR1 and LFSR2. The dither seed subaddress (0xC7) consists of a byte-wide seed for LFSR1 (bits 7:0) and a byte-wide seed for LFSR2 (bits 15:8). The seeds serve to define the starting point of each LFSR sequence, but not the feedback structure itself. Each linear feedback shift register (LFSR) is a 26-bit structure that runs off the digital audio processor (DAP) clock. For a maximum DAP clock frequency of 135.
0x7F S Slave Addr Ack Subaddr m Ack 0000 s xxx Ack b Subaddr m Ack 0000 s xxx Ack b Subaddr m Ack 0000 s xxx Ack b xxxxxxxx Ack xxxxxxxx l Ack xxxxxxx s Ack b xxxxxxxx Ack xxxxxxxx l Ack xxxxxxx s Ack b xxxxxxxx Ack xxxxxxxx l Ack xxxxxxx s Ack b xxxxxxxx Ack xxxxxxxx xxxxxxxx Ack xxxxxxxx 0x80 S Slave Addr Ack 0x81 S Slave Addr Ack Dither Block 0xC6 S Slave Addr Ack m Ack 0000 s xxx Ack b m 0000 s xxx Ack b Subaddr l Ack xxxxxxx s Ack b l Ack xxxxxxx s Ack b Distribut
When updating multiple TAS3103As with dither seeds, timing should be taken into account. The recommended seed update process is to load all TAS3103As with their seed values in less time than the minimum LFSR cycle time of 496.5 ms, and use the same set of seeds for all TAS3103As. Each TAS3103A immediately begins running, starting at the state set by the new seed, on receiving the new seed.
Quadratic Distribution 48-Bit DAP Data Word 47 0.375 ρ 8-Bit Headroom 0.25 40 39 32 Bit Sample 0.0625 −2W −W 0 W 2W 24 Bit Sample 20 Bit Sample 18 Bit Sample 16 Bit Sample 16-Bit Output SAP Word Size Output 28 27 Triangular Distribution 32-Bit Output SAP Word Size 24 22 20 16 ρ 0.5 0.25 8 −W 0 W Output 0 8-Bit Resolution Band Figure 3−32. Dither Data Magnitude (Gain = 1) 3.9.
(a) Auto-Correlation Plot − CH1 (b) Correlation Plot − CH1 and CH2 Figure 3−33. Triangular Dither Statistics, Case 1 Figure 3−34 presents plots of the autocorrelation and channel-to-channel correlation properties of the dither data stream when configured as quadratic distributed noise. Figure 3−34(a) is the circular autocorrelation of 16K samples of dither data collected from the TAS3103A. The audio signal level was set to zero and the dither data stream was inserted at the LSB+1 level of the output word.
selection of the quadratic distribution—50% of the 16K dither output samples are of value ±1 (0.5 × 12 ×16,000 = 8000) and 12.5% of the 16K dither output samples are ±2 (0.125 × 22 × 16,000 = 8000). Figure 3−34(b) is the circular correlation of 16K samples of dither data from CH2 and 16K samples of dither data from CH3. No points of correlation are in this plot, verifying that the two data streams are uncorrelated.
3.10 Output Crossbar Mixers The TAS3103A has three serial output ports—SDOUT1, SDOUT2, and SDOUT3. Each serial output port is assigned two processing nodes within the TAS3103A. One of the two nodes sources the left stereo data sample, and the other node sources the right stereo data sample. Figure 3−35 shows the assignment of these internal nodes to the serial output ports. Two cases are shown in Figure 3−35—discrete mode and TDM mode.
SDOUT1 Internal Processing Nodes L R LRCLK Time U L V R Internal Processing Nodes SDOUT1 U Node U SDOUT2 Internal Processing Nodes L R Nodes U & V V Nodes V & W LRCLK Time W L X R Nodes V, W & X W Nodes V, W, X & Y Nodes V, W, Y & Z X Nodes W, X, Y & Z Node X SDOUT3 Internal Processing Nodes L R LRCLK Time Y L Z R Y (a) Discrete Mode − For I2S Format, Polarity of LRCLK Opposite That Shown Z (b) TDM Mode Figure 3−35.
Mixer Gain Coefficient Subaddress Format m l S Slave Addr Ack Subaddr Ack 0000 s xxx Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxxs Ack b b z to U => 0x8F z to X => 0x8C z to V => 0x8E z to Y => 0x8B z to W => 0x8D z to Z => 0x8A U o z Delay Monaural CH 1 Dither Mixer Gain Coefficient Subaddress Format 0x84 m l S Slave Addr Ack Subaddr Ack 0000 s xxx Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxxs Ack b b y to U => 0x95 y to X => 0x92 y to V => 0x94 y to Y => 0x91 y to W => 0x93 y to Z => 0x90 V
3−58
4 Electrical Specifications 4.1 Absolute Maximum Ratings Over Operating Temperature Ranges (unless otherwise noted)† Supply voltage range: VDDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to 3.8 V A_VDDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to 3.8 V Input voltage range, VI: 3.3-V LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER VOH High-level output voltage VOL Low-level output voltage 3.3-V LVCMOS 1.8-V LVCMOS (XTALO) 3.3-V LVCMOS IOL = 4 mA 1.8-V LVCMOS (XTALO) IOL = 0.75 mA IOZ High-impedance output current Low-level input current(1) 3.3-V LVCMOS IIL High-level input current(2) 3.3-V LVCMOS IIH IDVDD Digital supply current TEST CONDITIONS IOH = −4 mA IOH = −0.55 mA Analog supply current TYP 1.
4.4 TAS3103A Timing Characteristics 4.4.1 Master Clock Signals Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS f(XTALI) Frequency, XTALI (1/tc(1)) 2.8 20 MHz f(MCLKI) tw(MCLKI) Frequency, MCLKI (1/tc(2)) 2.8 25 MHz Pulse duration, MCLKI high, see Note 1 HMCLKI − 25 HMCLKI HMCLKI + 25 MCLKI jitter 2.8 ns ±5 ns 25 MHz f(MCLKO) tr(MCLKO) Frequency, MCLKO (1/tc(3)) Rise time, MCLKO CL = 30 pF 9.
4.4.2 Control Signals Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER TEST CONDITIONS MIN 10 TYP MAX UNITS tw1(L) Pulse duration, RST low ns tpd1 tpd2 Propagation delay, PWRDN high to power-down state asserted See Note 1 µs Propagation delay, PWRDN low to power-down state deasserted See Note 2 µs NOTES: 1. The maximum worst-case value for tpd1 is given by t pd1_worst_case 80 + 4096 ) GPIOFSCOUNT ) LRCLK Microprocessor_Clock 2.
4.4.3 Serial Audio Port Slave-Mode Signals Over Recommended Operating Conditions (unless otherwise noted) TEST CONDITIONS PARAMETER MIN TYP MAX HSCLKIN 0.75 HSCLKIN fLRCLK tw(SCLKIN) Frequency, LRCLK (Fs) Pulse duration, SCLKIN high See Note 2 0.25 HSCLKIN fSCLKIN tcyc Frequency, SCLKIN See Note 1 32 Fs 25 Cycle time, SCLKIN See Note 1 40 1/32 Fs ns 15.
4.4.4 Serial Audio Port Master-Mode Signals Over Recommended Operating Conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP 8 MAX f(LRCLK) tr(LRCLK) Frequency LRCLK Rise time, LRCLK CL = 30 pF 11.4 ns tf(LRCLK) f(SCLKOUT) Fall time, LRCLK CL = 30 pF 11.2 ns Frequency (1/tcyc), SCLKOUT1/SCLKOUT2 See Note 1 25 MHz tr(SCLKOUT) tf(SCLKOUT) Rise time, SCLKOUT1/SCLKOUT2 CL = 30 pF 9.5 ns Fall time, SCLKOUT1/SCLKOUT2 CL = 30 pF 9.
4.4.5 Characteristics of the SDA and SCL I/O Stages for F/S-Mode I2C-Bus Devices PARAMETER TEST CONDITIONS STANDARD MODE FAST MODE MIN MAX MIN MAX 0.3 VDD –0.5 0.3 VDD N/A 0.7 VDD 0.05 VDD VIL VIH LOW-level input voltage –0.5 HIGH-level input voltage 0.
4.4.6 Characteristics of the SDA and SCL I/O Stages for F/S-Mode I2C-Bus Devices, (1) STANDARD MODE PARAMETER fSCL SCL clock frequency Hold time (repeated) START condition. After this period, the tHD-STA first clock pulse is generated. tLOW tHIGH FAST MODE MIN MAX MIN MAX 0 100 0 400 UNITS kHz 4 0.6 µs LOW period of the SCL clock 4.7 1.3 µs HIGH period of the SCL clock 4 0.6 µs 4.7 0.
A−1 1 1 Mix A to b Mix A to c Mix A to d Mix A to e Mix A to f Mix B to a Mix B to b Mix B to c Mix B to d Mix B to e Mix B to f Mix C to a Mix C to b Mix C to c Mix C to d Mix C to e Mix C to f Mix D to a Mix D to b Mix D to c Mix D to d Mix D to e Mix D to f Mix E to a Mix E to b Mix E to c Mix E to d Mix E to e Mix E to f Mix F to a 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19
A−2 1 1 Mix F to d Mix F to e Mix F to f Mix a to c Mix b to c Mix a to g Mix b to h Mix a to d via BQ and Rev/D Mix a to e via BQ and Rev/D Mix b to d via BQ and Rev/D Mix b to e via BQ and Rev/D Mix g to d via BQ Mix g to e via BQ Mix h to d via BQ Mix h to e via BQ Mix c to d via BQ Mix c to e via BQ Mix f to g and h a_de path, biquad 1 a_de path, biquad 2 a_de path, biquad 3 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33
A−3 a_de path, biquad 4 b_de path, biquad 1 b_de path, biquad 2 b_de path, biquad 3 b_de path, biquad 4 g_de path, biquad 1 g_de path, biquad 2 0x38 0x39 0x3A 0x3B 0x3C 0x3D REGISTER NAME 0x37 SUBADDRESS (0xSS) 5 5 5 5 5 5 5 NUMBER OF 4-BYTE WORDS 0x00, 0x00, 0x00, 0x00 0x00, 0x80, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 u(31:28)b0(27:24), b0 (23:16), b0(15:8), b0(7:0) u(31:28)b1(27:24), b1(23:16), b1(15:8), b1(7:0) u(31:28)b2(27:24), b2(23:16), b2(15:8), b2(7:0)
A−4 g_de path, biquad 3 g_de path, biquad 4 h_de path, biquad 1 h_de path, biquad 2 h_de path, biquad 3 h_de path, biquad 4 c_de path, biquad 1 0x3F 0x40 0x41 0x42 0x43 0x44 REGISTER NAME 0x3E SUBADDRESS (0xSS) 5 5 5 5 5 5 5 NUMBER OF 4-BYTE WORDS 0x00, 0x00, 0x00, 0x00 0x00, 0x80, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 u(31:28)b0(27:24), b0 (23:16), b0(15:8), b0(7:0) u(31:28)b1(27:24), b1(23:16), b1(15:8), b1(7:0) u(31:28)b2(27:24), b2(23:16), b2(15:8), b2(7:0)
A−5 c_de path, biquad 2 c_de path, biquad 3 c_de path, biquad 4 f_CH3 path, biquad 1 f_CH3 path, biquad 2 f_CH3 path, biquad 3 f_CH3 path, biquad 4 0x46 0x47 0x48 0x49 0x4A 0x4B REGISTER NAME 0x45 SUBADDRESS (0xSS) 5 5 5 5 5 5 5 NUMBER OF 4-BYTE WORDS 0x00, 0x00, 0x00, 0x00 0x00, 0x80, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 u(31:28)b0(27:24), b0 (23:16), b0(15:8), b0(7:0) u(31:28)b1(27:24), b1(23:16), b1(15:8), b1(7:0) u(31:28)b2(27:24), b2(23:16), b2(15:8), b2(7:
A−6 CH1 biquad 1 CH1 biquad 2 CH1 biquad 3 CH1 biquad 4 CH1 biquad 5 CH1 biquad 6 0x50 0x51 0x52 0x53 0x54 f_CH3 path, reverb gain Rg1 f_CH3 path, reverb gain Rg0 b_de path, reverb gain Rg1 b_de path, reverb gain Rg0 a_de path, reverb gain Rg1 a_de path, reverberation (reverb) gain Rg0 REGISTER NAME 0x4F 0x4E 0x4D 0x4C SUBADDRESS (0xSS) 5 5 5 5 5 5 2 2 2 NUMBER OF 4-BYTE WORDS 0x00, 0x00, 0x00, 0x00 0x00, 0x80, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 u(31:
A−7 CH1 biquad 7 CH1 biquad 8 CH1 biquad 9 CH1 biquad 10 CH1 biquad 11 CH1 biquad 12 CH2 biquad 1 0x56 0x57 0x58 0x59 0x5A 0x5B REGISTER NAME 0x55 SUBADDRESS (0xSS) 5 5 5 5 5 5 5 NUMBER OF 4-BYTE WORDS 0x00, 0x00, 0x00, 0x00 0x00, 0x80, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 u(31:28)b0(27:24), b0 (23:16), b0(15:8), b0(7:0) u(31:28)b1(27:24), b1(23:16), b1(15:8), b1(7:0) u(31:28)b2(27:24), b2(23:16), b2(15:8), b2(7:0) 0x00, 0x00, 0x00, 0x00 u(31:28)b2(27:24), b2(
A−8 CH2 biquad 2 CH2 biquad 3 CH2 biquad 4 CH2 biquad 5 CH2 biquad 6 CH2 biquad 7 CH2 biquad 8 0x5D 0x5E 0x5F 0x60 0x61 0x62 REGISTER NAME 0x5C SUBADDRESS (0xSS) 5 5 5 5 5 5 5 NUMBER OF 4-BYTE WORDS 0x00, 0x00, 0x00, 0x00 0x00, 0x80, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 u(31:28)b0(27:24), b0 (23:16), b0(15:8), b0(7:0) u(31:28)b1(27:24), b1(23:16), b1(15:8), b1(7:0) u(31:28)b2(27:24), b2(23:16), b2(15:8), b2(7:0) 0x00, 0x00, 0x00, 0x00 u(31:28)b2(27:24), b2(23:
A−9 CH2 biquad 9 CH2 biquad 10 CH2 biquad 11 CH2 biquad 12 CH3 biquad 1 CH3 biquad 2 CH3 biquad 3 0x64 0x65 0x66 0x67 0x68 0x69 REGISTER NAME 0x63 SUBADDRESS (0xSS) 5 5 5 5 5 5 5 NUMBER OF 4-BYTE WORDS 0x00, 0x00, 0x00, 0x00 0x00, 0x80, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 u(31:28)b0(27:24), b0 (23:16), b0(15:8), b0(7:0) u(31:28)b1(27:24), b1(23:16), b1(15:8), b1(7:0) u(31:28)b2(27:24), b2(23:16), b2(15:8), b2(7:0) 0x00, 0x00, 0x00, 0x00 u(31:28)b2(27:24), b2(
A−10 CH3 biquad 4 CH3 biquad 5 CH3 biquad 6 CH3 biquad 7 CH3 biquad 8 CH3 biquad 9 CH3 biquad 10 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 REGISTER NAME 0x6A SUBADDRESS (0xSS) 5 5 5 5 5 5 5 NUMBER OF 4-BYTE WORDS 0x00, 0x00, 0x00, 0x00 0x00, 0x80, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 u(31:28)b0(27:24), b0 (23:16), b0(15:8), b0(7:0) u(31:28)b1(27:24), b1(23:16), b1(15:8), b1(7:0) u(31:28)b2(27:24), b2(23:16), b2(15:8), b2(7:0) 0x00, 0x00, 0x00, 0x00 u(31:28)b2(27:24), b2(2
A−11 Bass and treble bypass 1 0x73 Mix w to m Mix j to i Mix l to k Mix n to m Mix j to o via DRC mult 0x78 0x79 0x7A 0x7B 0x7C Mix dither1 to o Mix dither2 to p Mix dither3 to q Mix delay3 to o Mix delay3 to p Mix o to r Mix o to s Mix p to r 0x80 0x81 0x82 0x83 0x84 0x85 0x86 DRC bypass 3 Mix n to q via DRC mult 0x7F 0x7E DRC bypass 2 Mix l to p via DRC mult DRC bypass 1 Mix v to k 0x77 0x7D Mix u to i Bass and treble inline 3 Bass and treble bypass 3 0x76 0x75 B
A−12 1 1 1 1 Mix r to s and t Mix z to Z Mix z to Y Mix z to X Mix z to W Mix z to V Mix z to U Mix y to Z Mix y to Y Mix y to X Mix y to W Mix y to V Mix y to U Mix x to Z Mix x to Y Mix x to X Mix x to W Mix x to V Mix x to U Mix r to Z Mix r to Y Mix r to X Mix r to W Mix r to V Mix r to U CH1 loudness log2 G CH1 loudness log2 O CH1 loudness G CH1 loudness O 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9
A−13 CH2 loudness O CH2 loudness biquad CH3 loudness log2 G CH3 loudness log2 O CH3 loudness G CH3 loudness O CH3 loudness biquad CH1/CH2 DRCE ae 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB3 0xB2 1 CH2 loudness G 0xA9 0xAA 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 u(31:28)b1(27:24), b1(23:16), b1(15:8), b1(7:0) u(31:28)b2(27:24), b2(23:16), b2(15:8), b2(7:0) 0x00, 0x00, 0x00, 0x00 LO31:24(31:24), LO23:16(23:16), LO15:8(15:8), LO7:0(7:0) u(31:28)G(27:24), G(23:16), G(15:8), G(7:0) 0x
A−14 0xBC 0xBB 0xBA 0xB9 0xB8 0xB7 0xB6 0xB5 0xB4 SUBADDRESS (0xSS) Spectrum analyzer BQ1 Spectrum analyzer 1-asa 5 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x80, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 u(31:28)a2(27:24), a2(23:16), a2(15:8), a2(7:0) u(31:28)b0(27:24), b0 (23:16), b0(15:8), b0(7:0) u(31:28)b1(27:24), b1(23:16), b1(15:8), b1(7:0) u(31:28)b2(27:24), b2(23:16), b2(15:8), b2(7:0) 0x00, 0x00, 0x00, 0x00 0x00, 0x80, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0
A−15 Spectrum analyzer BQ2 Spectrum analyzer BQ3 Spectrum analyzer BQ4 Spectrum analyzer BQ5 Spectrum analyzer BQ6 Spectrum analyzer BQ7 Spectrum analyzer BQ8 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 REGISTER NAME 0xBD SUBADDRESS (0xSS) 5 5 5 5 5 5 5 NUMBER OF 4-BYTE WORDS 0x00, 0x00, 0x00, 0x00 0x00, 0x80, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 u(31:28)b0(27:24), b0 (23:16), b0(15:8), b0(7:0) u(31:28)b1(27:24), b1(23:16), b1(15:8), b1(7:0) u(31:28)b2(27:24), b2(23:16), b2(1
A−16 Spectrum analyzer BQ10 Dither LFSR1 mix 0xC5 0xC6 1 1 1 1 1 1 1 1 1 Factory test Mix G to g Mix G to f Mix G to Y Mix H to h Mix H to f Mix H to Z Mix d to aa Mix e to aa Reserved (2) Reserved (2) Reserved (2) Reserved (2) Reserved (2) Reserved (2) Reserved (2) Reserved (2) Reserved (2) Reserved (2) Reserved (2) Reserved (2) 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD3 0xD5 0xD6 0xD8 0xD9 0xDB 0xDC 0xDD 0xDA 0xD7 0xD4 0xD2 Factory test 1 1 1 1 1 1
A−17 1 1 1 1 1 1 1 1 2 Reserved (2) Reserved (2) Reserved (2) Reserved (2) Reserved (2) Reserved (2) Reserved (2) Reserved (2) Reserved (2) Reserved (2) Reserved (2) Watchdog timer enable Factory test (2) Factory test (2) GPIO port I/O value GPIO parameters Master mute/unmute Vol, T and B slew rates CH1 volume (5.23 precision) CH2 volume (5.23 precision) CH3 volume (5.
A−18 SA7(7:0) SA8(7:0) SA9(7:0) SA10(7:0) Spectrum analyzer output 7 Spectrum analyzer output 8 Spectrum analyzer output 9 Spectrum analyzer output 10 Flag register VU meter output 2 (SA6) 0.25 SA6(7:0) Spectrum analyzer output 6 CONTENTS (u Indicates Unused Bits) u(7:1)VolBusy(0), 1 = busy SA6(7:0) SA5(7:0) SA5(7:0) Spectrum analyzer output 5 0.5 SA4(7:0) Spectrum analyzer output 4 VU meter output 1 (SA5) SA3(7:0) Spectrum analyzer output 3 SA1(7:0) SA2(7:0) 2.
A−19 H G F E D C B A c b a f h g 4 BQ 4 BQ 4 BQ 4 BQ 4 BQ 4 BQ Rev Del Rev Del Rev Del e d A.
A−20 Reset I2C Data Clocks TAS3103ADBT NOTE: 0.01-µF capacitors must be placed as close as possible to the device pins. All other capacitors should be placed after the 0.01-µF so that the distance between the capacitors and the device pins is minimized. A.3 TAS3103A Simplified Application Schematic Diagram 0.47 µF 0.
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