Datasheet

T0146-10
WCLK
BCLK
DIN
t (WS)
h
t (WS)
h
t (BCLK)
L
t
r
t
f
t (DI)
S
t (BCLK)
H
t (DI)
h
t (WS)
S
t (WS)
S
TAS2521
SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013 www.ti.com
3.5.4 DSP Timing in Slave Mode
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
IOVDD = 1.8V IOVDD = 3.3 V
PARAMETER UNIT
MIN MAX MIN MAX
t
H
(BCLK) BCLK high period 35 35 ns
t
L
(BCLK) BCLK low period 35 35 ns
t
s
(WS) WCLK setup 8 8 ns
t
h
(WS) WCLK hold 8 8 ns
t
s
(DI) DIN setup 8 8 ns
t
h
(DI) DIN hold 8 8 ns
t
r
Rise time 4 4 ns
t
f
Fall time 4 4 ns
Figure 3-4. DSP Timing in Slave Mode
12 ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TAS2521