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TAS2521

www.ti.com

SLAS687A –FEBRUARY 2013–REVISED FEBRUARY 2013

Digital Input Class-D Speaker Amplifier with Embedded miniDSP and mono headphone

amplifier

Check for Samples: TAS2521

1 INTRODUCTION

1.1 Features

• Digital Input Mono Speaker Amp

1.2 Applications

• Instruction-Programmable Embedded miniDSP

• Portable Audio Devices

• Supports 8-kHz to 192-kHz Sample Rates

• White goods

• Mono Class-D BTL Speaker Driver (2 W Into

• Portable Navigation Devices

4 Ω or 1.7 W Into 8 Ω)

• Mono Headphone Driver

1.3 Description

• Two Single-Ended Inputs With Output Mixing

and Level Control

The TAS2521 is a low power digital input speaker

• Embedded Power-on-Reset

amp with support for 24-bit digital I2S data mono

• Integrated LDO

playback.

• Built-in Digital Audio Processing Blocks With

In addition to driving a speaker amp upto 4-Ω, the

User-Programmable Biquad Filters

device also features a mono headphone driver and a

• Integrated PLL Used for Programmable Digital

fully programmable miniDSP for signal processing.

Audio Processor

The digital audio data format is programmable to

• I

S, Left-Justified, Right-Justified, DSP, and

work with popular audio standard protocols (I

TDM Audio Interfaces

left/right-justified) in master, slave, DSP and TDM

• I

C and SPI control with auto-increment

modes. The fully programmable miniDSP can support

• Full Power-Down Control

several functions such equalization for audio, multi-

• Power Supplies:

band DRC, tone generation and several other user

– Analog: 1.5 V–1.95 V

defined functions. An on-chip PLL provides the high-

– Digital Core: 1.65 V–1.95 V

speed clock needed by the digital signal-processing

– Digital I/O: 1.1 V–3.6 V

block. The volume level can be controlled by register

– Class-D: 2.7 V–5.5 V (SPKVDD ≥ AVDD)

control. The audio functions are controlled using the

• 24-Pin QFN Package (4mm × 4mm)

C™ serial bus or SPI bus. The device includes an

on-board LDO that runs off the speaker power supply

to handle all internal device analog and digital power

needs. The included POR as power-on-resetcircuit

reliably resets the device into its default state so no

external reset is required at normal usage; however,

the device does have a reset pin for more complex

system initialization needs. The device also includes

two analog inputs for mixing and muxing in both

speaker and headphone analog paths.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

Summary of content (35 pages)

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TAS2521 www.ti.com SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 Digital Input Class-D Speaker Amplifier with Embedded miniDSP and mono headphone amplifier Check for Samples: TAS2521 1 INTRODUCTION 1.1 Features 1 • • • • • • • • • • • • • • • Digital Input Mono Speaker Amp Instruction-Programmable Embedded miniDSP Supports 8-kHz to 192-kHz Sample Rates Mono Class-D BTL Speaker Driver (2 W Into 4 Ω or 1.
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TAS2521 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TAS2521 www.ti.com SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 2 PACKAGE AND SIGNAL DESCRIPTIONS 2.1 Package/Ordering Information PRODUCT PACKAGE PACKAGE DESIGNATOR OPERATING TEMPERATURE RANGE TAS2521 QFN-24 RGE –40°C to 85°C 2.
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TAS2521 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com Table 2-1. RGE PIN FUNCTIONS (continued) PIN I/O (1) DESCRIPTION NAME NO. MISO 17 O GPIO/DOUT 18 I/O/Z SCL/SSZ 19 I Either I2C Input Serial Clock or SPI Chip Select Signal depending on SPI_SEL state SDA/MOSI 20 I Either I2C Serial Data Input or SPI Serial Data Input depending on SPI_SEL state. SCLK 21 I Serial clock for SPI interface IOVDD 22 PWR I/O Power Supply, 1.1V - 3.
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TAS2521 www.ti.com 3.3 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) AVDD (1) Power-supply voltage range DVDD SPKVDD Referenced to AVSS (2) Referenced to DVSS (2) (1) Referenced to SPKVSS IOVDD MIN NOM MAX 1.5 1.8 1.95 1.65 1.8 1.95 2.7 (2) Referenced to IOVSS (2) 1.1 5.5 1.8 UNIT V 3.
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TAS2521 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com Electrical Characteristics (continued) At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS, PLL = Off PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Audio DAC – Stereo Single-Ended Headphone Output Load = 16Ω (single-ended), Input & Output CM = 0.
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TAS2521 www.ti.com SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 Electrical Characteristics (continued) At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.
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TAS2521 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com Electrical Characteristics (continued) At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS, PLL = Off PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG BYPASS TO CLASS-D SPEAKER AMPLIFIER Device Setup BTL measurement, DRIVER GAIN = 6 dB, LOAD = 4 Ω (DIFFERENTIAL), 50 pF, input signal frequency fi = 1 KHz Voltage Gain Input common-mode = 0.
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TAS2521 www.ti.com 3.5 3.5.1 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 Timing Characteristics I2S/LJF/RJF Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. WCLK tr td(WS) BCLK tf tS(DI) th(DI) DIN T0145-10 PARAMETER td(WS) ts(DI) th(DI) tr tf IOVDD = 1.8 V MIN MAX 45 8 8 25 25 WCLK delay DIN setup DIN hold Rise time Fall time IOVDD = 3.
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TAS2521 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com I2S/LJF/RJF Timing in Slave Mode 3.5.2 All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. WCLK tr th(WS) tS(WS) tH(BCLK) BCLK tL(BCLK) tf tS(DI) DIN th(DI) T0145-11 IOVDD = 1.
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TAS2521 www.ti.com 3.5.3 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 DSP Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. WCLK td(WS) td(WS) tf BCLK tr tS(DI) DIN th(DI) T0146-09 IOVDD = 1.8 V MIN MAX 45 8 8 25 25 PARAMETER td(WS) ts(DI) th(DI) tr tf WCLK delay DIN setup DIN hold Rise time Fall time IOVDD = 3.3 V MIN MAX 45 6 6 10 10 UNIT ns ns ns ns ns Figure 3-3.
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TAS2521 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 3.5.4 www.ti.com DSP Timing in Slave Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. WCLK tS(WS) tS(WS) th(WS) th(WS) tf tL(BCLK) BCLK tr tS(DI) tH(BCLK) DIN th(DI) T0146-10 IOVDD = 1.
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TAS2521 www.ti.com 3.5.5 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 I2C Interface Timing All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. SDA tBUF tLOW tr tHIGH tf tHD;STA SCL tHD;STA tSU;DAT tHD;DAT STO tSU;STO tSU;STA STA STA STO T0295-02 PARAMETER fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb SCL clock frequency Hold time (repeated) START condition.
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TAS2521 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 3.5.6 www.ti.com SPI Interface Timing SS S t t Lead t t Lag td sck SCLK t sckl tf tr t sckh t v(DOUT) t dis MISO MSB OUT BIT 6 . . . 1 LSB OUT ta t hi t su MOSI MSB IN BIT 6 . . . 1 LSB IN Figure 3-6. SPI Interface Timing Diagram Timing Requirements At 25°C, DVDD = 1.8V Table 3-1. SPI Interface Timing PARAMETER TEST CONDITION IOVDD=1.8V MIN (1) IOVDD=3.
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TAS2521 www.ti.com SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 4 Typical Performance 4.1 Class D Speaker Driver Performance 20 0 0 ±20 ±20 ±40 ±40 Amplitude (dB) Amlitude (dB) 20 ±60 ±80 ±100 ±80 ±100 ±120 ±120 ±140 ±140 ±160 ±160 ±180 ±180 0 4000 8000 12000 16000 Frequency (Hz) 20000 100 0 8000 12000 16000 20000 Frequency (Hz) C002 Figure 4-2. AINL To Speaker FFT Amplitude at 0 dBFS vs Frequency (4 Ω Load) 100.
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TAS2521 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com 90 80 Efficiency (%) 70 60 50 40 SPKVDD = 2.7 V SPKVDD = 3 V SPKVDD = 3.3 V SPKVDD = 3.6 V SPKVDD = 4.2 V SPKVDD = 5.5 V 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 Output Power (mWatt) C007 Figure 4-7.
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TAS2521 www.ti.com 4.2 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 HP Driver Performance 20 0 0 ±20 ±20 ±40 ±40 Amplitude ( dB) Amplitude ( dB) 20 ±60 0dBFS ±80 ±100 ±120 ±60 ±100 ±120 ±140 ±140 ±160 ±160 ±180 ±180 0 4000 8000 12000 16000 20000 Frequency (Hz) 0 ±10 ±20 ±20 ±30 ±30 THDN (dB) ±10 ±50 CM=0.75V,AVDD=1.5V ±60 CM=0.75V,AVDD=1.8V 12000 ±40 CM=0.75V, Series4 AVDD=1.95V ±70 CM=0.9V, Series5 AVDD=1.8V ±80 CM=0.9V, Series6 AVDD=1.95V CM=0.
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TAS2521 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com 5 Application Overview The TAS2521 offers a wide range of configuration options. Figure 1-1 shows the simplified functional blocks of the device. 5.1 Typical Circuit Configuration +1.8VA SVDD IOVDD 22PF 2.7k 0.1PF 0.1PF 22PF 2.7k AVSS AVDD LDO_SEL SPKVSS SPKVDD GPIO/DOUT HOST PROCESSOR SDA/MOSI SCL/SSZ 8-: or 4-: Speaker MCLK SPKP SPKM TAS2521 WCLK DIN BCLK Headphone jack RST HPOUT 0.
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TAS2521 www.ti.com 5.2 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 Circuit Configuration with Internal LDO SVDD IOVDD 22PF 2.7k 0.1PF 10PF 0.1PF 0.1PF 22PF 2.7k AVSS AVDD DVSS DVDD LDO_SEL SPKVSS SPKVDD GPIO/DOUT HOST PROCESSOR SDA/MOSI SCL/SSZ 8-: or 4-: Speaker MCLK WCLK DIN SPKP SPKM TAS2521 BCLK RST HPOUT 0.1PF 47PF AINL AINR Analog Input 0.1PF MISO SCLK SPI_SEL IOVDD IOVSS IOVDD 0.1PF 10PF Figure 5-2. Application Schematics for LDO 5.3 5.3.
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TAS2521 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 5.3.3 www.ti.com Multifunction Pins Table 5-1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO). Table 5-1.
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TAS2521 www.ti.com 5.5.1 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 Analog Inputs AINL and AINR AINL (pin 3 or C2) and AINR (pin 4 or B2) are inputs to Mixer P and Mixer M along with the DAC output. Also AINL and AINR can be configured inputs to HP driver. Page1 / register 12 provides control signals for determining the signals routed through Mixer P, Mixer M and HP driver.
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TAS2521 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com The signal-processing blocks available are: • First-order IIR • Scalable number of biquad filters The processing blocks are tuned for common cases and can achieve high image rejection or low group delay in combination with various signal-processing effects such as audio effects and frequency shaping. The available first-order IIR and biquad filters have fully user-programmable coefficients. Table 5-2.
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TAS2521 www.ti.com SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 Table 5-3. AVDD LDO Settings Page-1, Register 2, D(5:4) LDO Output 00 1.8 V 01 1.6 V 10 1.7 V 00 1.5 V For more detailed information see the TAS2521 Application Reference Guide (SLAU456). 5.6.5 POR TAS2521 has a POR (Power On Reset) function. This function insures that all registers are automatically set to defaults when a proper power up sequence is executed.
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TAS2521 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com 5.6.7.2.1 I2C Control Mode The TAS2521 supports the I2C control protocol, and will respond to the I2C address of 0011 000. I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
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TAS2521 www.ti.com SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 5.6.7.5.1 Software Software development for the TAS2521 is supported through TI's comprehensive PurePath™ Studio software development environment, a powerful, easy-to-use tool designed specifically to simplify software development on Texas Instruments miniDSP audio platforms.
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TAS2521 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com 6 Register Map 6.1 Register Map Summary Table 6-1. Summary of Register Map Decimal Hex DESCRIPTION PAGE NO. REG. NO. PAGE NO. REG. NO.
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TAS2521 www.ti.com SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 Table 6-1. Summary of Register Map (continued) Decimal Hex DESCRIPTION PAGE NO. REG. NO. PAGE NO. REG. NO.
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TAS2521 SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com Table 6-1. Summary of Register Map (continued) Decimal Hex DESCRIPTION PAGE NO. REG. NO. PAGE NO. REG. NO. 45 - 52 0 0x2D-0x34 0x00 Page Select Register 45 - 52 1-7 0x2D-0x34 0x01 - 0x07 Reserved.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS2521IRGET Package Package Pins Type Drawing VQFN RGE 24 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 12.4 Pack Materials-Page 1 4.25 B0 (mm) K0 (mm) P1 (mm) 4.25 1.15 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS2521IRGET VQFN RGE 24 250 210.0 185.0 35.
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