Datasheet
TAS2505
SLAS778A –FEBRUARY 2013–REVISED FEBRUARY 2013
www.ti.com
3 ELECTRICAL SPECIFICATIONS
3.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
MIN MAX
AVDD to AVSS –0.3 2.2 V
DVDD to DVSS –0.3 2.2 V
SPKVDD to SPKVSS –0.3 6 V
IOVDD to IOVSS –0.3 3.9 V
Digital input voltage IOVSS – 0.3 IOVDD + 0.3 V
Analog input voltage AVSS – 0.3 AVDD + 0.3 V
Operating temperature range –40 85 °C
Storage temperature range –55 150 °C
Junction temperature (T
J
Max) 105 °C
QFN Power dissipation(with thermal pad soldered to board) (T
J
Max – T
A
) / θ
JA
W
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3.2 THERMAL INFORMATION
TAS2505
THERMAL METRIC
(1)
UNITS
RGE (24 PINS)
θ
JA
Junction-to-ambient thermal resistance 32.2
θ
JCtop
Junction-to-case (top) thermal resistance 30.0
θ
JB
Junction-to-board thermal resistance 9.2
°C/W
ψ
JT
Junction-to-top characterization parameter 0.3
ψ
JB
Junction-to-board characterization parameter 9.2
θ
JCbot
Junction-to-case (bottom) thermal resistance 2.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
3.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD
(1)
Referenced to AVSS
(2)
1.5 1.8 1.95
Power-supply voltage range
DVDD Referenced to DVSS
(2)
1.65 1.8 1.95
V
SPKVDD
(1)
Referenced to SPKVSS
(2)
2.7 5.5
IOVDD Referenced to IOVSS
(2)
1.1 1.8 3.6
Speaker impedance Load applied across class-D output pins (BTL) 4 Ω
Headphone impedance AC-coupled to R
L
16 Ω
Analog audio full-scale input
V
I
AVDD = 1.8 V, single-ended 0.5 V
RMS
voltage
Line output load impedance
AC-coupled to R
L
10 kΩ
(in half drive ability mode)
MCLK
(3)
Master clock frequency IOVDD = DVDD = 1.8V 50 MHz
SCL SCL clock frequency 400 kHz
(1) To minimize battery-current leakage, the SPKVDD voltage level should not be below the AVDD voltage level.
(2) All grounds on board are tied together, so they should not differ in voltage by more than 0.2 V maximum for any combination of ground
signals. By use of a wide trace or ground plane, ensure a low-impedance connection between AVSS and DVSS.
(3) The maximum input frequency should be 50 MHz for any digital pin used as a general-purpose clock.
4 ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated
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