Datasheet

RST
AINR
SPI_SEL
LDO_SEL
AINL
AVSS
HPOUT
SPKM
SPKVSS
AVDD
WCLK
SPKVDD
SPKP
BCLK
MCLK
MISO
SDA/MOSI
DIN
GPIO/DOUT
IOVDD SCL/SSZ DVSS SCLK DVDD
23 2124 22 20 19
17
16
14
18
15
13
5
3
6
1
4
2
111098 127
TAS2505
www.ti.com SLAS778A –FEBRUARY 2013–REVISED FEBRUARY 2013
2.2 Device Information
RGE PACKAGE
(TOP VIEW)
Table 2-1. RGE PIN FUNCTIONS
PIN
I/O
(1)
DESCRIPTION
NAME NO.
SPI_SEL 1 I Selects between SPI and I2C digital interface modes; (1 = SPI mode) (0 = I2C mode)
RST 2 I Reset for logic, state machines, and digital filters; asserted LOW.
AINL 3 I Analog single-ended line left input
AINR 4 I Analog single-ended line right input
HPOUT 5 O Headphone and Lineout Driver Output
AVSS 6 GND Analog Ground, 0V
AVDD 7 PWR Analog Core Supply Voltage, 1.5V - 1.95V, tied internally to the LDO output
LDO_SEL 8 I Select Pin for LDO; ties to either SPKVDD or SPKVSS
SPKM 9 O Class-D speaker driver inverting output
SPKVDD 10 PWR Class-D speaker driver power supply
SPKVSS 11 PWR Class-D speaker driver power supply ground supply
SPKP 12 O Class-D speaker driver non-inverting output
DIN 13 I Audio Serial Data Bus Input Data
WCLK 14 I/O Audio Serial Data Bus Word Clock
BCLK 15 I/O Audio Serial Data Bus Bit Clock
MCLK 16 I Master CLK Input / Reference CLK for CLK Multiplier - PLL (On startup PLLCLK = CLKIN)
MISO 17 O SPI Serial Data Output
GPIO/DOUT 18 I/O/Z GPIO / Audio Serial Bus Output
SCL/SSZ 19 I Either I2C Input Serial Clock or SPI Chip Select Signal depending on SPI_SEL state
SDA/MOSI 20 I Either I2C Serial Data Input or SPI Serial Data Input depending on SPI_SEL state.
SCLK 21 I Serial clock for SPI interface
IOVDD 22 PWR I/O Power Supply, 1.1V - 3.6V
DVDD 23 PWR Digital Power Supply, 1.65V - 1.95V
DVSS 24 GND Digital Ground, 0V
(1) I = Input, O = Output, GND = Ground, PWR = Power, Z = High Impedance
Copyright © 2013, Texas Instruments Incorporated PACKAGE AND SIGNAL DESCRIPTIONS 3
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