Datasheet

DIN
BCLK
WCLK
MCLK
SPKVSS
AVDDAVSS
LDO_SEL
SPKVDD
SCL/SSZ
SDA/MOSI
GPIO/DOUT
RST
IOVDD IOVSS
AINL
SPKP
SPKM
HOST PROCESSOR
0.1PF
22PF
SVDD
0.1PF
22PF
8-: or
4-:
Speaker
IOVDD
AINR
Analog Input
TAS2505
HPOUT
Headphone jack
MISO
SPI_SEL
SCLK
IOVDD
0.1PF
0.1PF
2.7k
2.7k
47PF
DVDDDVSS
0.1PF
10PF
0.1PF 10PF
TAS2505
www.ti.com SLAS778A –FEBRUARY 2013–REVISED FEBRUARY 2013
5.2 Circuit Configuration with Internal LDO
Figure 5-2. Application Schematics for LDO
5.3 Device Connections
5.3.1 Digital Pins
Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins
have a default function, and also can be reprogrammed to cover alternative functions for various
applications.
The fixed-function pins are RST LDO_SEL and the SPI_SEL pin, which are HW control pins. Depending
on the state of SPI_SEL, the two control-bus pins SCL/SSZ and SDA/MOSI are configured for either I
2
C
or SPI protocol.
Other digital IO pins can be configured for various functions via register control. An overview of available
functionality is given in Section 5.3.3.
5.3.2 Analog Pins
Analog functions can also be configured to a large degree. For minimum power consumption, analog
blocks are powered down by default. The blocks can be powered up with fine granularity according to the
application needs.
Copyright © 2013, Texas Instruments Incorporated Application Overview 19
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