Datasheet

SRC4392
SBFS029D –DECEMBER 2005–REVISED DECEMBER 2012 www.ti.com
Register 2F: SRC Control Register 3
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
OWL1 OWL0 0 0 0 0 0 0
OWL[1:0] SRC Output Word Length
These bits select the word length for the SRC output data. The word length reduction is
performed by utilizing triangular PDF dithering.
OWL1 OWL0 SRC Output Word Length
0 0 24 Bits (Default)
0 1 20 Bits
1 0 18 Bits
1 1 16 Bits
Note: When the SRC is selected as the output data source for Port A or B and the data format
for the port is set to Right-Justified, the proper word length must be selected in the Port A or B
control registers such that it matches the corresponding SRC output data word length set by the
OWL0 and OWL1 bits.
Register 30: SRC Control Register 4
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
These bits are utilized to configure the SRC digital output attenuation for the Left Channel when the TRACK bit
in register 0x2D is set to 0. The attenuation setting for the Left channel also applies to the Right channel when
TRACK bit in register 0x2D is set to 1.
Output Attenuation (dB) = –N × 0.5, where N = AL[7:0]
DEC
.
Register 31: SRC Control Register 5
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
These bits are utilized to configure the SRC digital output attenuation for the Right Channel when the TRACK
bit in register 0x2D is set to 0.
Output Attenuation (dB) = –N × 0.5, where N = AR[7:0]
DEC
.
Register 32: SRC Ratio Readback Register (Read-Only)
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
SRI4 SRI3 SRI2 SRI1 SRI0 SRF10 SRF9 SRF8
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