Datasheet

SRC4392
SBFS029D –DECEMBER 2005–REVISED DECEMBER 2012 www.ti.com
Register 2C: Burst Preamble PD Low-Byte Status Register (Read-Only)
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
PD07 PD06 PD05 PD04 PD03 PD02 PD01 PD00
Register 2D: SRC Control Register 1
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
0 TRACK 0 MUTE SRCCLK1 SRCCLK0 SRCIS1 SRCIS0
SRCIS[1:0] SRC Input Data Source
These bits select the input data source for the SRC.
SRCIS1 SRCIS0 Input Source
0 0 Port A (Default)
0 1 Port B
1 0 DIR
1 1 Reserved
SRCCLK
SRC Reference Clock Source
[1:0]
These bits select the reference clock source for the SRC.
SRCCLK1 SRCCLK0 Reference Clock Source
0 0 MCLK (Default)
0 1 RXCKI
1 0 RXCKO
1 1 Reserved
MUTE SRC Output Soft Mute Function
This bit enables or disables the SRC output soft mute function.
MUTE Mute Function
0 Mute Disabled (Default)
1 Mute enabled; output data set to all zeros.
TRACK SRC Digital Output Attenuation Tracking
This bit enables or disables left and right channel attenuation tracking.
TRACK Output Attenuation Tracking
Tracking Disabled (Default)
0 The Left and Right channel attenuation is programmed separately using
registers 0x30 and 0x31, respectively.
Tracking Enabled
1 The Left channel attenuation setting is also used for the Right channel. The
Right channel tracks the Left channel setting.
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