Datasheet

Y
X
Y
X
L R L R
L R L R
R L R L
AES3BitStream
DIRSYNC
LRCK,I2SFormat(input)
LRCK,LeftorRight
JustifiedFormats(input)
±5% ±5%
DataSliporRepeatmayoccurwhentheLRCKedgesindicatedarewithinthe 5%window.±
SRC4392
www.ti.com SBFS029D –DECEMBER 2005–REVISED DECEMBER 2012
Figure 93. DIR Output Slip/Repeat (OSLIP) Behavior
Register 16: Receiver Interrupt Mask Register 1
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
MCSCRC MPARITY MVBIT MBPERR MQCHG MUNLOCK MQCRC MRBTI
MCSCRC Channel Status CRC Error Interrupt Mask
MCSCRC CRC Interrupt
0 Masked (Default)
1 Enabled
MPARITY Parity Error Interrupt Mask
MPARITY Parity Error Interrupt
0 Masked (Default)
1 Enabled
MVBIT Validity Error Interrupt Mask
MVBIT Validity Error Interrupt
0 Masked (Default)
1 Enabled
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