Datasheet

SRC4392
www.ti.com SBFS029D –DECEMBER 2005–REVISED DECEMBER 2012
Register 13: Receiver Status Register 1 (Read-Only)
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
0 0 0 0 0 0 RXCKR1 RXCKR0
RXCKR[1:0] Maximum Available Recovered Clock Rate
These two bits indicate the maximum available RXCKO clock rate based upon the DIR detection
circuitry, which determines the frame rate of the incoming AES3-encoded bit stream. Based upon
the estimated frame rate, a maximum rate for the recovered clock output (RXCKO) is determined
and output from PLL2, as well as being loaded into the RXCKR0 and RXCKR1 status bits.
The status of the RXCKR0 and RXCKR1 bits may be utilized to determine the programmed value
for the PLL2 output clock divider, set by the RXCKOD0 and RXCKOD1 bits in control register
0x0E.
RXCKR1 RXCKR0 Maximum Available RXCKO Rate
0 0 Clock rate not determined.
0 1 128f
S
1 0 256f
S
1 1 512f
S
Register 14: Receiver Status Register 2 (Read-Only)
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
CSCRC PARITY VBIT BPERR QCHG UNLOCK QCRC RBTI
Note: Status bits must be unmasked in control register 0x16 in order for the status interrupts to be generated.
CSCRC Channel Status CRC Status
CSCRC CRC Status
0 No Error
1 CRC Error Detected
PARITY Parity Status
PARITY Parity Status
0 No Error
1 Parity Error Detected
VBIT Validity Bit Status
VBIT Validity Bit
0 Valid Audio Data Indicated
1 Non-Valid Data Indicated
BPERR Bipolar Encoding Error Status
BPERR Bipolar Encoding Status
0 No Error
1 Bipolar Encoding Error Detected
Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback 65
Product Folder Links: SRC4392